HW-AFX-FF1760-500-G Xilinx Inc, HW-AFX-FF1760-500-G Datasheet
HW-AFX-FF1760-500-G
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Virtex-5 LX FPGA Prototype Platform User Guide UG222 (v1.1) April 18, 2008 R P/N 0402510-02 ...
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Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit ...
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Table of Contents Preface: About This Guide Additional Documentation Additional Support Resources Typographical Conventions Online Document . . . . . . . . . . . . . . . . . . . . . . . . ...
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Virtex-5 LX FPGA Prototype Platform R UG222 (v1.1) April 18, 2008 ...
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R About This Guide This user guide describes the features and operation of the Virtex platform and provides instructions to configure chains of FPGAs and serial PROMs. Complete and up-to-date documentation for the Virtex-5 LX FPGA prototype platform is available ...
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Preface: About This Guide • Virtex-5 FPGA System Monitor User Guide The System Monitor functionality available in all the Virtex-5 devices is outlined in this guide. • Virtex-5 FPGA Packaging Specifications This specification includes the tables for device/package combinations and ...
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R Virtex-5 LX FPGA Prototype Platform Overview The Virtex-5 FPGA prototype platform and demonstration boards enable designers to investigate and experiment with the features of Virtex-5 FPGAs. This user guide describes the features and operation of the Virtex-5 LX FPGA ...
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... For information about the Virtex-5 family of FPGA devices, including product highlights, data sheets, user guides, and application notes, see the Virtex-5 website at www.xilinx.com/virtex5. Additional information is available from the data sheets and application notes from the component manufacturers. 8 (HW-AFX-FF324-500-G) (HW-AFX-FF676-500-G (HW-AFX-FF1153-500-G) (HW-AFX-FF1760-500-G) www.xilinx.com Virtex-5 LX FPGA Prototype Platform UG222 (v1.1) April 18, 2008 R ...
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R Block Diagram Figure 1 shows a block diagram of the board. X-Ref Target - Figure 1 Upstream System ACE Interface Connector System Monitor User LEDs VBATT Downstream System ACE Interface Connector Power Bus and Switches 5V Jack -or- 5V ...
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Detailed Description Detailed Description The Virtex-5 LX FPGA prototype platform board is shown in sections on the pages following the figures contain details on each feature. Note: The image might not reflect the current revision of the board. X-Ref Target ...
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R Table 1: Voltage Ranges Label VCCINT VCCO VCCAUX VCC1V8 Off Position In the OFF position, the power switch disables all modes of powering the DUT. Power Enable Jumpers For each power supply there are headers (J20, J19, and J21) ...
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Detailed Description 3. Configuration Ports The configuration port header (J17) supports all Virtex-5 device configuration modes. For use with a Parallel Cable III or Parallel Cable IV cable, the header supports Slave Serial and JTAG configuration modes. Table 2 shows ...
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R 4. JTAG Chain J41 header both devices in the JTAG chain. header. X-Ref Target - Figure 3 Table 4: J41 Jumper Settings J41 Pin Jumpers 5. JTAG Termination Header When connecting another board to ...
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Detailed Description 6. Upstream/Downstream Connectors 6a. Upstream System ACE Interface Connector The upstream System ACE interface connector (P1) can be used to configure the DUT (Figure 4). Any JTAG configuration stream can source this connector. For example, a System ACE ...
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R 6c. Upstream Interface Connector The upstream interface connector (P2) is used to configure the DUT in select map or slave- serial mode of another prototype platform board. X-Ref Target - Figure 6 Virtex-5 LX FPGA Prototype Platform UG222 (v1.1) ...
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Detailed Description 6d. Downstream Interface Connector The downstream interface connector (P4) passes serial configuration information to the DUT in the downstream prototype platform board X-Ref Target - Figure 7 7. Prototyping Area The prototyping area accommodates 0.10-inch spaced ICs. The ...
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R 10. Oscillator Sockets The board has four crystal oscillator sockets (X1, X2, X3, X4), all wired for standard LVTTL-type oscillators. These sockets connect to the DUT clock pads termination resistors can be changed by the user. The oscillator sockets ...
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Detailed Description 12. DUT Socket The DUT socket (U1) contains the user FPGA. The DUT must be oriented using the P1 indicator on the board. Caution! pin damage, always use the vacuum tool provided when inserting or removing the Virtex-5 ...
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R 14. User LEDs (Active-High) There are 16 active-High user LEDs on the board. Before configuration, the LEDs reflect the status of the configuration mode pins. During configuration, the LEDs are in a high- impedance condition. After configuration, the LEDs ...
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Detailed Description 15. PROGRAM Switch This active-Low PROGRAM switch (SW1) grounds the DUT’s PROG pin when pressed. This action clears the DUT. 16. RESET Switch (Active-Low) The RESET switch (SW2) connects to a standard I/O pin on the DUT, allowing ...
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R 20. SPI Interface The SPI interface is a four-wire, synchronous serial data bus configuration. The interface utilizes a 64-Mb STMicroelectronics low-voltage, serial Flash memory device (U10), part number M25P64, which can be used for FPGA configuration or to hold ...
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Detailed Description Table 12: BPI Pins (Cont’d) Label DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 22 Pin ...
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R Table 12: BPI Pins (Cont’d) Label WE_N WP_N ADV_N RST_N CE_N WAIT CLK OE_N J47 is a three-pin header that allows users to connect the OE signal to VCC FPGA pin. Jumper pin ...
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Detailed Description 22. Configuration Mode Pins The three jumpers on J17 control the configuration mode pins M0-M2. These pins set the configuration mode for the FPGA and determine the direction of CCLK (see Figure 8). A jumper across both columns ...
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R References 1. DS202, Virtex-5 FPGA Data Sheet: DC and Switching Characteristics 2. DS123, Platform Flash ISPROM Data Sheet 3. UG191, Virtex-5 FPGA Configuration User Guide 4. UG196, Virtex-5 FPGA RocketIO GTP Transceiver User Guide 5. iMPACT Software Tool Documents ...