HW-AFX-FF1760-500-G Xilinx Inc, HW-AFX-FF1760-500-G Datasheet - Page 23

• Manufacturer Part Number: HW-AFX-FF1760-500-G
• Description: BOARD DEV VIRTEX 5 FF1760
• Manufacturer: Xilinx Inc
• Type: FPGAr

Specifications of HW-AFX-FF1760-500-G

• Contents: *
• For Use With/related Products: Virtex™-5 LX FF1760
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Virtex-5 LX FPGA Prototype Platform
UG222 (v1.1) April 18, 2008
R
Table 12: BPI Pins (Cont’d)
J47 is a three-pin header that allows users to connect the OE signal to VCC or to an FPGA
pin. Jumper pin 1 to 2 connects the OE signal to VCC. Jumper pin 2 to 3 connects the OE
signal to an FPGA IOB.
J54 allows users to connect the revision select (RS) signals to the highest address lines of the
BPI device. Jumper pins 1 to 3 and pins 2 to 4 connect address 23 and address 24 to FPGA
IOBs. Jumper pins 3 to 5 and pins 4 to 6 connect RS0 and RS1 to the highest address lines
of the BPI device. Refer to the Virtex-5 FPGA Configuration User Guide
information on how the RS signals may be applied in a user’s application.
ADV_N
RST_N
WE_N
WP_N
Label
CE_N
WAIT
OE_N
CLK
FF324
Table 12
U16
P10
A2
G4
F6
E6
F4
P9
www.xilinx.com
shows the corresponding FPGA pin.
Pin Number for Package Type
FF676
AA10
AB15
AA9
E7
L5
L4
L3
F7
FF1153
AD20
AE12
AE13
A3
C2
C3
B3
B1
Detailed Description
[Ref 3]
for more
FF1760
AL29
AK14
AK15
G2
E2
F2
F1
J2
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