HW-AFX-FF1760-500-G Xilinx Inc, HW-AFX-FF1760-500-G Datasheet - Page 12

• Manufacturer Part Number: HW-AFX-FF1760-500-G
• Description: BOARD DEV VIRTEX 5 FF1760
• Manufacturer: Xilinx Inc
• Type: FPGAr

Specifications of HW-AFX-FF1760-500-G

• Contents: *
• For Use With/related Products: Virtex™-5 LX FF1760
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Detailed Description
12
3. Configuration Ports
PC4 JTAG Configuration Interface
The configuration port header (J17) supports all Virtex-5 device configuration modes. For
use with a Parallel Cable III or Parallel Cable IV cable, the header supports Slave Serial and
JTAG configuration modes.
Table 2
Parallel Cable III or Parallel Cable IV flying-wire cable.
Table 2: Serial Mode
Table 3
Parallel Cable III or Parallel Cable IV flying-wire cable.
Table 3: JTAG Mode
The JTAG configuration port (J1) for the board allows for device programming and FPGA
debug. This interface can be used with a Parallel Cable III or Parallel Cable IV cable for
JTAG programming and debugging via the JTAG configuration port.
Configuration Port Header
Configuration Port Header
shows Serial mode connectivity between the configuration port header and a
shows JTAG mode connectivity between the configuration port header and a
VCC3V3
DONE
PROG
CCLK
VCC3
GND
GND
TDO
INIT
INIT
TMS
TCK
DIN
TDI
www.xilinx.com
Parallel Cable III/IV Pins
Parallel Cable III Pins
CCLK
PROG
GND
GND
VCC
VCC
TDO
D/P
DIN
TMS
TCK
TDI
Virtex-5 LX FPGA Prototype Platform
Parallel Cable IV Pins
UG222 (v1.1) April 18, 2008
GND
VCC
TMS
TDO
INIT
TCK
TDI
R