AD9748ACP-PCB Analog Devices Inc, AD9748ACP-PCB Datasheet - Page 14

• Manufacturer Part Number: AD9748ACP-PCB
• Description: BOARD EVAL FOR AD9748ACP
• Manufacturer: Analog Devices Inc
• Series: TxDAC®r

Specifications of AD9748ACP-PCB

• Rohs Status: RoHS non-compliant
• Number Of Dac's: 1
• Number Of Bits: 8
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 210M
• Data Interface: Parallel
• Settling Time: 11ns
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9748

AD9748
DAC TIMING
Input Clock and Data Timing Relationship
Dynamic performance in a DAC is dependent on the
relationship between the position of the clock edges and the
time at which the input data changes. The AD9748 is rising
edge triggered, and so exhibits dynamic performance sensitivity
when the data transition is close to this edge. In general, the
goal when applying the AD9748 is to make the data transition
close to the falling clock edge. This becomes more important as
the sample rate increases. Figure 21 shows the relationship of
SFDR to clock placement with different sample rates. Note that
at the lower sample rates, more tolerance is allowed in clock
placement, while at higher rates, more care must be taken.
Sleep Mode Operation
The AD9748 has a power-down function that turns off the output
current and reduces the supply current to less than 6 mA over the
specified supply range of 2.7 V to 3.6 V and the temperature range.
This mode can be activated by applying a Logic Level 1 to the
SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 Ω
AVDD. This digital input also contains an active pull-down
circuit that ensures that the AD9748 remains enabled if this
input is left disconnected. The AD9748 takes less than 50 ns to
power down and approximately 5 μs to power back up.
POWER DISSIPATION
The power dissipation, P
several factors that include the:
•
•
•
•
The power dissipation is directly proportional to the analog
supply current, I
is directly proportional to I
insensitive to f
Power supply voltages (AVDD, CLKVDD, and DVDD)
Full-scale current output (I
Update rate (f
Reconstructed digital input waveform
Figure 21. SFDR vs. Clock Placement @ f
80
75
70
65
60
55
50
45
40
35
30
0
CLOCK
AVDD
2
CLOCK
.
, and the digital supply current, I
)
(f
CLOCK PLACEMENT (ns)
D
CLOCK
4
, of the AD9748 is dependent on
OUTFS
= 165 MSPS)
, as shown in Figure 22, and is
OUTFS
6
)
OUT
= 20 MHz and 50 MHz
20MHz SFDR
50MHz SFDR
8
10
DVDD
12
. I
AVDD
Rev. A | Page 14 of 24
Conversely, I
waveform, f
as a function of full-scale sine wave output ratios (f
for various update rates with DVDD = 3.3 V.
35
30
25
20
15
10
11
20
18
16
14
12
10
10
0
0
8
6
4
2
0
9
8
7
6
5
4
3
2
1
0.01
2
0
CLOCK
DVDD
4
Figure 24. I
Figure 23. I
, and digital supply DVDD. Figure 23 shows I
is dependent on both the digital input
50
6
Figure 22. I
CLKVDD
DVDD
8
RATIO (f
100
f
vs. Ratio @ DVDD = 3.3 V
CLOCK
I
vs. f
OUTFS
125MSPS
210MSPS
165MSPS
10
65MSPS
AVDD
DIFF
CLOCK
0.1
OUT
PECL
(MSPS)
(mA)
SE
12
/f
vs. I
CLOCK
and Clock Mode
150
OUTFS
14
)
16
200
18
OUT
/f
CLOCK
20
250
1
DVDD
)