ad73311l Analog Devices, Inc., ad73311l Datasheet
ad73311l
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ad73311l Summary of contents
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... The final channel bandwidth can be reduced, and signal-to-noise ratio improved, by external digital filtering in a DSP engine. The AD73311L is suitable for a variety of applications in the speech and telephony area, including low bit rate, high quality compression, speech enhancement, recognition and synthesis. ...
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... PGA = 6 dB Total Harmonic Distortion PGA = 0 dB PGA = 6 dB Intermodulation Distortion Idle Channel Noise Crosstalk 1 (AVDD = DVDD = 2 3.3 V; DGND = AGND = kHz unless otherwise noted MIN MAX AD73311LA Min Typ Max Unit 1.08 1.2 1. ppm/°C Ω 145 1.08 1.2 1. kΩ ...
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... V |IOUT| ≤ 100 µA V µ See Table I MCLK SE ON Comments 1 YES REFOUT Disabled 1 YES REFOUT Disabled 0 NO REFOUT Disabled YES MCLK Active Levels Equal and DVDD 0 NO Digital Inputs Static and Equal DVDD AD73311L ...
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... AD73311L Parameter Condition V REFCAP V REFOUT ADC Maximum Input Range at V Nominal Reference Level DAC Maximum Voltage Output Swing Single-Ended Differential Nominal Voltage Output Swing Single-Ended Differential Output Bias Voltage TIMING CHARACTERISTICS Limit at Parameter T = – +105 C A Clock Signals 24 ...
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... V – dBm0 D15 D14 D15 –10 –85 –15 –5 0 3.17 AD73311L D15 D1 D0 D15 –75 –65 –55 –45 –35 –25 –15 – – dBm0 3.17 IN D14 ...
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... NOTES 0.3' Small Outline IC (SOIC Shrink Small Outline Package (SSOP Thin Small Shrink Outline Package (TSSOP). 2 The AD73311L evaluation board features a cascade of two codecs interfaced to an ADSP-2185L DSP. The board features a DSP software monitor which allows interface serial port. WARNING! SE ...
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... When SE is brought high, the control and data regis- ters of the SPORT are at their original values (before SE was brought low); however, the timing counters and other internal registers are at their reset values. PIN FUNCTION DESCRIPTIONS AD73311L ...
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... BW Bandwidth. CRx A Control Register where placeholder for an alphabetic character (A–E). There are five read/ write control registers on the AD73311L—desig- nated CRA through CRE. CRx:n A bit position, where placeholder for a numeric character (0–7), within a control register; where placeholder for an alphabetic charac- ter (A– ...
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... Sigma-delta converters employ a technique known as over- sampling, where the sampling rate is many times the highest frequency of interest. In the case of the AD73311L, the initial sampling rate of the sigma-delta modulator is DMCLK/8. The main effect of oversampling is that the quantization noise is spread over a very wide bandwidth (Figure 6a) ...
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... B FINAL INTER Decimation Filter The digital filter used in the AD73311L carries out two impor- tant functions. Firstly, it removes the out-of-band quantization noise, which is shaped by the analog modulator and secondly, it decimates the high frequency bitstream to a lower rate 15-bit word. The antialiasing decimation filter is a sinc-cubed digital filter ...
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... MCLK to internal DMCLK divider and serial clock divider. The divider rates are controlled by the setting of Control Register B. The AD73311L features a master clock divider that allows users the flexibility of dividing externally available high frequency DSP or CPU clocks to gener- ...
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... The control register bank consists of six read/write registers, each eight bits wide. Table IX shows the control register map for the AD73311L. The first two control registers, CRA and CRB, are reserved for controlling the SPORT. They hold settings for parameters such ...
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... If the address is not zero decremented and the control word is passed out of the device via the serial output. This 3-bit field is used to select one of the five control registers on the AD73311L. This 8-bit field holds the data that written to or read from the selected register provided the address fi ...
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... AD73311L CONTROL REGISTER A 7 RESET Bit CONTROL REGISTER B 7 CEE Bit CONTROL REGISTER C 7 – Bit Table XI. Control Register A Description DC2 DC1 DC0 SLB Name Description DATA/PGM Operating Mode (0 = Program ...
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... Reserved Must Be Programmed to Zero (0) Reserved Must Be Programmed to Zero (0) Reserved Must Be Programmed to Zero (0) Reserved Must Be Programmed to Zero (0) SEEN Single-Ended Enable (0 = Disabled Enabled) INV Input Invert (0 = Disabled Enabled) ALB Analog Loopback of Output to Input (0 = Disabled Enabled) AD73311L IGS1 IGS0 DA1 DA0 – ...
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... AD73311L Operating Modes There are five operating modes available on the AD73311L. Two of these—Digital Loop-Back and Sport Loop-Back—are provided as diagnostic modes with the other three, Program, Data and Mixed Program/Data, being available for general purpose use. The device configuration—register settings—can be changed only in Program and Mixed Program/Data Modes ...
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... DATA (CONTROL) WORD (DEVICE 1) SE SCLK SDOFS(2) SDO(2) SAMPLE WORD (DEVICE 2) SDOFS(1) SDIFS(2) SDO(1) SAMPLE WORD (DEVICE 1) SDI(2) SDIFS(1) SDI(1) DATA (CONTROL) WORD (DEVICE 2) SAMPLE WORD (DEVICE 1) DATA (CONTROL) WORD (DEVICE 1) SAMPLE WORD (DEVICE 1) DATA (CONTROL) WORD (DEVICE 2) DATA (CONTROL) WORD (DEVICE 1) AD73311L ...
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... TIME FILTER AD73311L Cascade Operation The AD73311L has been designed to support up to eight codecs in a cascade connected to a single serial port (see Figure 37). The SPORT interface protocol has been designed so that device addressing is built into the packet of information sent to the device. ...
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... PERFORMANCE As the AD73311L is designed to provide high performance, low cost conversion important to understand the means by which this high performance can be achieved in a typical applica- tion. This section will, by means of spectral graphs, outline the typical performance of the device and highlight some of the ...
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... AD73311L The AD73311L also features direct sampling at the lower rate of 8 kHz. This is achieved by the use of extended decimation registers within the decimator block, which allows for the increased word growth associated with the higher effective oversampling ratio. Figure 17 details the spectrum kHz test tone converted kHz rate ...
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... FREQUENCY – the AD73311L can be operated at 8 kHz (see Figure 21 kHz sampling rates, which make it particularly suited for voiceband processing important to understand the action of the interpolator’s Sinc3 response. As was the case with the encoder section, if the output signal’s frequency response is not bounded by the Nyquist frequency it may be necessary to perform some initial digital fi ...
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... AD73311L. The internal inverting op amps on the AD73311L are specifically designed to interface to the ADC’s SC input stage. The AD73311L’s on-chip 38 dB preamplifier can be enabled when there is not enough gain in the input circuit; the preampli- fi ...
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... If the ADC is being connected in single-ended mode, the AD73311L should be programmed for single-ended mode using the SEEN and INV bits of CRF, and the inputs connected as shown in Figure 28. When operated in single-ended input mode, the AD73311L can multiplex one of the two inputs to the ADC input, as shown in Figures 28 and 29. 0.1 F 10k ...
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... The circuit of Figure 33 shows a scheme for doing this. LOAD R LOAD Digital Interfacing The AD73311L is designed to easily interface to most common DSPs. The SCLK, SDO, SDOFS, SDI and SDIFS must be CONTINUOUS connected to the SCLK, DR, RFS, DT and TFS pins of the TIME LOW-PASS DSP respectively ...
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... However, because the resolution of the AD73311’s ADC is high, and the noise levels from the AD73311L are so low, care must be taken with regard to grounding and layout. The printed circuit board that houses the AD73311L should be designed so the analog and digital sections are separated and confi ...
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... Tx and Rx SPORT interrupts to a single one at each sample interval. The user also knows where each sample is stored. The alternative is to handle a larger number of SPORT interrupts (twice as many in the case of a single AD73311L) while also having some status flags to indicate where each new sample comes from (or is destined for). ...
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... The DSP’s transmit interrupt is enabled. imask = b#0001000000; At each occurrence of an SDOFS pulse, the DSP’s transmit buffer contents are sent to the SDI pin of the AD73311L. This also causes a subsequent DSP Tx interrupt which transfers the initialization word, pointed to by the circular buffer pointer, to the Tx buffer ...
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... If the AD73311L is used in a cascade of two or more codec units important to observe some restrictions in the sequence of sending initialization words to the two codecs preferable to send groups of control words for the corresponding control registers in each codec and it is essential to send the control words in descending order— ...
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... Configuring an AD73311L to Operate in Data Mode This section describes the typical sequence of control words that are required to be sent to an AD73311L to set it up for data mode operation. In this sequence, Registers B, C and A are programmed before the device enters data mode. This description panel refers to Table XIX ...
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... AD73311L Configuring an AD73311L to Operate in Mixed Mode This section describes a typical sequence of control words that would be sent to an AD73311L to configure it for operation in mixed mode not intended definitive initialization sequence, but will show users the typical input/output events that occur in the programming and Operation Phases description panel refers to Table XX ...
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... CRC-CH1 10000010xxxxxxxx READBACK CH 1 1100001011111001 DON’T CARE xxxxxxxxxxxxxxxx ADC RESULT CH1 ???????????????? DON’T CARE xxxxxxxxxxxxxxxx DAC WORD CH 1 0111111111111111 AD73311L DSP Rx DON’T CARE xxxxxxxxxxxxxxxx OUTPUT CH1 0000000000000000 DON’T CARE xxxxxxxxxxxxxxxx DON’T CARE xxxxxxxxxxxxxxxx ADC RESULT CH1 0000000000000000 DON’ ...
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... Data Mode This section describes the typical sequence of control words that are required to be sent to a cascade of two AD73311Ls to set them up for data mode operation. In this sequence Registers B, C and A are programmed before the device enters data mode. This description panel refers to Table XXI. ...
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... ADC RESULT CH1 ADC RESULT CH2 ???????????????? ???????????????? DAC WORD CH 2 ADC RESULT CH1 0111111111111111 ???????????????? DAC WORD CH 1 DAC WORD CH 2 1000000000000000 0111111111111111 AD73311L DSP Rx DON’T CARE xxxxxxxxxxxxxxxx OUTPUT CH2 0000000000000000 OUTPUT CH1 0000000000000000 DON’T CARE xxxxxxxxxxxxxxxx OUTPUT CH2 1011100100001011 ...
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... DSP to use autobuffered transfers of two words). The transmit register of the DSP is loaded with the control word destined for Device 2. This generates a transmit frame-sync (TFS) that is input to the SDIFS input of the AD73311L (Device 1) to indi- cate the start of transmission. In Step 4, Device 1 now contains the Control Word destined for Device 2. The address fi ...
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... DON’T CARE DON’T CARE xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx DAC WORD CH 2 DON’T CARE 0111111111111111 xxxxxxxxxxxxxxxx DAC WORD CH 1 DAC WORD CH 2 1000000000000000 0111111111111111 AD73311L DSP Rx DON’T CARE xxxxxxxxxxxxxxxx OUTPUT CH2 0000000000000000 OUTPUT CH1 0000000000000000 DON’T CARE xxxxxxxxxxxxxxxx DON’T CARE xxxxxxxxxxxxxxxx DON’ ...
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... AD73311L APPENDIX E DAC Timing Control Example The AD73311’s DAC is loaded from the DAC register contents just before the ADC register contents are loaded to the serial register (SDOFS going high). This default DAC load position can be advanced in time to occur earlier with respect to the SDOFS going high ...