EPM3256A ALTERA [Altera Corporation], EPM3256A Datasheet
EPM3256A
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EPM3256A Summary of contents
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... Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance EPM3064A EPM3128A 1,250 2,500 64 128 4 66 4.5 5.0 2.8 3.3 3.1 3.4 222.2 192.3 MAX 3000A Programmable Logic Device Family ® architecture (see TM packages EPM3256A 5,000 256 158 7.5 5.2 4.8 126.6 Data Sheet Table 1) EPM3512A 10,000 512 32 208 7.5 5.6 4.7 116.3 1 ...
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MAX 3000A Programmable Logic Device Family Data Sheet ...and More Features General MAX 3000A devices are low–cost, high–performance devices based on the Altera MAX architecture. Fabricated with advanced CMOS technology, Description the EEPROM–based MAX 3000A devices operate with a 3.3-V ...
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... PLCC EPM3032A 34 EPM3064A 34 EPM3128A EPM3256A EPM3512A Note: (1) When the IEEE Std. 1149.1 (JTAG) interface is used for in–system programming or boundary–scan testing, four I/O pins become JTAG pins. MAX 3000A devices use CMOS EEPROM cells to implement logic functions. The user–configurable MAX 3000A architecture accommodates a variety of independent combinatorial and sequential logic functions ...
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MAX 3000A Programmable Logic Device Family Data Sheet MAX 3000A devices contain 32 to 512 macrocells, combined into groups of 16 macrocells called logic array blocks (LABs). Each macrocell has a programmable–AND/fixed–OR array and a configurable register with independently programmable ...
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... Output Enables (1) I/O Control I/O Block I/O Control I/O Block Note: (1) EPM3032A, EPM3064A, EPM3128A, and EPM3256A devices have six output enables. EPM3512A devices have 10 output enables. Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet LAB Macrocells ...
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MAX 3000A Programmable Logic Device Family Data Sheet Macrocells MAX 3000A macrocells can be individually configured for either sequential or combinatorial logic operation. Macrocells consist of three functional blocks: logic array, product–term select matrix, and programmable register. Figure 2. MAX ...
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Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet For registered functions, each macrocell flipflop can be individually programmed to implement operation with programmable clock control. The flipflop can be bypassed for combinatorial operation. ...
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MAX 3000A Programmable Logic Device Family Data Sheet Shareable Expanders Each LAB has 16 shareable expanders that can be viewed as a pool of uncommitted single product terms (one from each macrocell) with inverted outputs that feed back into the ...
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Figure 4. MAX 3000A Parallel Expanders Unused product terms in a macrocell can be allocated to a neighboring macrocell. 36 Signals 16 Shared from PIA Expanders Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet The Altera development system ...
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MAX 3000A Programmable Logic Device Family Data Sheet Programmable Interconnect Array Logic is routed between LABs on the PIA. This global bus is a programmable path that connects any signal source to any destination on the device. All MAX 3000A ...
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... Figure 6. I/O Control Block of MAX 3000A Devices PIA Note: (1) EPM3032A, EPM3064A, EPM3128A, and EPM3256A devices have six output enables. EPM3512A devices have 10 output enables. Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet to Other I/O Pins from Macrocell to PIA When the tri–state buffer control is connected to ground, the output is tri-stated (high impedance), and the I/O pin can be used as a dedicated input. When the tri– ...
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MAX 3000A Programmable Logic Device Family Data Sheet In–System MAX 3000A devices can be programmed in–system via an industry– standard four–pin IEEE Std. 1149.1-1990 (JTAG) interface. In-system Programma- programmability (ISP) offers quick, efficient iterations during design development and debugging cycles. ...
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IEEE Std. 1149.1 (JTAG) Boundary–Scan Support Table 4. MAX 3000A JTAG Instructions JTAG Instruction SAMPLE/PRELOAD Allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern ...
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... EPM3064A 0001 0111 0000 0110 0100 EPM3128A 0001 0111 0001 0010 1000 EPM3256A 0001 0111 0010 0101 0110 EPM3512A 0001 0111 0101 0001 0010 The most significant bit (MSB the left. The least significant bit (LSB) for all JTAG IDCODEs is 1. ...
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Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Figure 7 shows the timing information for the JTAG signals. Figure 7. MAX 3000A JTAG Waveforms TMS TDI t JCP t t JCH JCL TCK t JPZX TDO t JSSU ...
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MAX 3000A Programmable Logic Device Family Data Sheet Programmable MAX 3000A devices offer a power–saving mode that supports low-power operation across user–defined signal paths or the entire device. This Speed/Power feature allows total power dissipation to be reduced by 50% ...
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Design Security Generic Testing Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Open–Drain Output Option MAX 3000A devices provide an optional open–drain (equivalent to open-collector) output for each I/O pin. This open–drain output enables the device to provide ...
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MAX 3000A Programmable Logic Device Family Data Sheet Operating Conditions Table 9. MAX 3000A Device Absolute Maximum Ratings Symbol Parameter V Supply voltage input voltage output current, per pin OUT T Storage temperature STG ...
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Table 10. MAX 3000A Device Recommended Operating Conditions Symbol Parameter V Supply voltage for internal logic and CCINT input buffers V Supply voltage for output drivers, CCIO 3.3–V operation Supply voltage for output drivers, 2.5–V operation V Supply voltage during ...
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MAX 3000A Programmable Logic Device Family Data Sheet Table 12. MAX 3000A Device Capacitance Symbol Parameter C Input pin capacitance IN C I/O pin capacitance I/O Notes to tables: (1) See the Operating Requirements for Altera Devices Data (2) Minimum ...
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Power Sequencing & Hot–Socketing Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Figure 9. Output Drive Characteristics of MAX 3000A Devices 3.3 V 150 100 Typical I O Output Current (mA 2.5 V 150 100 ...
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MAX 3000A Programmable Logic Device Family Data Sheet Timing Model MAX 3000A device timing can be analyzed with the Altera software, with a variety of popular industry–standard EDA simulators and timing analyzers, or with the timing model shown in devices ...
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Figure 11. MAX 3000A Switching Waveforms t & t < 2 ns. Inputs are R F driven for a logic high and 0 V for a logic low. All timing characteristics are measured at 1.5 V. Shared ...
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... MAX 3000A Programmable Logic Device Family Data Sheet Tables 13 EPM3256A, and EPM3512A timing information. Table 13. EPM3032A External Timing Parameters Symbol Parameter t Input to non– PD1 registered output t I/O input to non– PD2 registered output t Global clock setup SU time t Global clock hold time ...
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Table 14. EPM3032A Internal Timing Parameters (Part Symbol Parameter t Input pad and buffer delay IN t I/O input pad and buffer IO delay t Shared expander delay SEXP t Parallel expander delay PEXP t Logic array ...
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MAX 3000A Programmable Logic Device Family Data Sheet Table 14. EPM3032A Internal Timing Parameters (Part Symbol Parameter t Register clear time CLR t PIA delay PIA t Low–power adder LPA Table 15. EPM3064A External Timing Parameters Symbol ...
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Table 16. EPM3064A Internal Timing Parameters (Part Symbol Parameter t Input pad and buffer delay IN t I/O input pad and buffer IO delay t Shared expander delay SEXP t Parallel expander delay PEXP t Logic array ...
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MAX 3000A Programmable Logic Device Family Data Sheet Table 16. EPM3064A Internal Timing Parameters (Part Symbol Parameter t PIA delay PIA t Low–power adder LPA Table 17. EPM3128A External Timing Parameters Symbol Parameter t Input to non– ...
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Table 18. EPM3128A Internal Timing Parameters (Part Symbol Parameter t Input pad and buffer delay IN t I/O input pad and buffer IO delay t Shared expander delay SEXP t Parallel expander delay PEXP t Logic array ...
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... MAX 3000A Programmable Logic Device Family Data Sheet Table 18. EPM3128A Internal Timing Parameters (Part Symbol Parameter t PIA delay PIA t Low–power adder LPA Table 19. EPM3256A External Timing Parameters Symbol Parameter t Input to non–registered PD1 output t I/O input to non–registered PD2 output ...
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... Table 20. EPM3256A Internal Timing Parameters Symbol Parameter t Input pad and buffer delay IN t I/O input pad and buffer delay IO t Shared expander delay SEXP t Parallel expander delay PEXP t Logic array delay LAD t Logic control array delay LAC t Internal output enable delay IOE ...
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MAX 3000A Programmable Logic Device Family Data Sheet Table 21. EPM3512A External Timing Parameters Symbol Parameter t Input to non-registered output PD1 t I/O input to non-registered PD2 output t Global clock setup time SU t Global clock hold time ...
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Table 22. EPM3512A Internal Timing Parameters (Part Symbol Parameter t Shared expander delay SEXP t Parallel expander delay PEXP t Logic array delay LAD t Logic control array delay LAC t Internal output enable delay IOE t ...
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MAX 3000A Programmable Logic Device Family Data Sheet Table 22. EPM3512A Internal Timing Parameters (Part Symbol Parameter t Low-power adder LPA Notes to tables: (1) These values are specified under the recommended operating conditions, as shown in ...
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... Constants (shown in Table 23. MAX 3000A I Equation Constants CC Device EPM3032A EPM3064A EPM3128A EPM3256A EPM3512A The I calculation provides an I CCINT conditions using a pattern of a 16–bit, loadable, enabled, up/down counter in each LAB with no output load. Actual I during operation because this measurement is sensitive to the actual pattern in the device and the environmental operating conditions ...
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MAX 3000A Programmable Logic Device Family Data Sheet Figure 12 vs. Frequency for MAX 3000A Devices CC EPM3032A Room Temperature High Speed Typical Active (mA ...
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... MAX 3000A Programmable Logic Device Family Data Sheet Figure 13. I vs. Frequency for MAX 3000A Devices CC EPM3128A 210 180 150 Typical I CC 120 Active (mA EPM3256A 350 300 250 Typical I CC 200 Active (mA) 150 100 50 0 EPM3512A 600 500 400 Typical I ...
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MAX 3000A Programmable Logic Device Family Data Sheet Device See the Altera web site (http://www.altera.com) or the Altera Digital Library for pin–out information. Pin–Outs Figures 14 MAX 3000A devices. Figure 14. 44–Pin PLCC/TQFP Package Pin–Out Diagram Package outlines not drawn ...
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... Package outline not drawn to scale. Figure 16. 144–Pin TQFP Package Pin–Out Diagram Package outline not drawn to scale Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Pin 1 EPM3064A EPM3128A Pin 26 . Indicates location of Pin 1 Pin 1 EPM3128A EPM3256A Pin 37 Pin 76 Pin 51 Pin 109 Pin 73 39 ...
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... MAX 3000A Programmable Logic Device Family Data Sheet Figure 17. 208–Pin PQFP Package Pin–Out Diagram Package outline not drawn to scale Pin 1 Pin EPM3256A EPM3512A Pin 157 Pin 105 Altera Corporation ...
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... The following changes were made in the MAX 3000A Programmable Logic Device Data Sheet version 3.1: Updated timing information in Note (10) Updated of Table Figure Table 1 for the EPM3256A device. 12. A1 Ball Pad Corner 13. 41 ...
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MAX 3000A Programmable Logic Device Family Data Sheet Version 3.0 The following changes were made in the MAX 3000A Programmable Logic Device Data Sheet version 3.0: 101 Innovation Drive San Jose, CA 95134 Copyright © 2002 Altera Corporation. All rights ...