IDT70824 Integrated Device Technology, IDT70824 Datasheet
IDT70824
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IDT70824 Summary of contents
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... Description The IDT70824 is a high-speed 4K x 16-Bit Sequential Access Random Access Memory (SARAM). The SARAM offers a single-chip solution to buffer data sequentially on one port, and be accessed randomly (asyn- chronously) through the other port. The device has a Dual-Port RAM ...
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... This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. The IDT70824 is packaged in a 80-pin Thin Quad Flatpack (TQFP) or 84-pin Pin Grid Array (PGA). Military grade product is manufactured in compliance with the latest revision of MIL-PRF-38535 QML, making it ideally suited to military temperature applications demanding the highest level of performance and reliability ...
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... IDT70824S/L High-Speed Sequential Access Random Access Memory Pin Descriptions: Random Access Port SYMBOL NAME A -A Address Lines 0 11 I/O -I/O Inputs/Outputs Chip Enable CMD Control Register Enable R/W Read/Write Enable OE Output Enable LB, UB Lower Byte, Upper Byte Enables V Power Supply CC GND Ground ...
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... IDT70824S/L High-Speed Sequential Access Random Access Memory Absolute Maximum Ratings Symbol Rating Commercial & Industrial (2) V Terminal Voltage -0.5 to +7.0 TERM with Respect to GND T Temperature -55 to +125 BIAS Under Bias Storage -65 to +150 T STG Temperature DC Output 50 I OUT Current NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...
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... IDT70824S/L High-Speed Sequential Access Random Access Memory DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter Test Condition CE and CE I Dynamic Operating Current Outputs Disabled SCE = V (5) (Both Ports Active MAX SCE and ...
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... IDT70824S/L High-Speed Sequential Access Random Access Memory Data Retention Power Down/Up Waveform (Random and Sequential Port CDR SCLK SCE NOTES : 1. SCE is synchronized to the sequential clock input. 2. CMD > 0.2V. CC DATA OUT 347Ω Figure 1. AC Output Test Load ...
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... IDT70824S/L High-Speed Sequential Access Random Access Memory Truth Table I: Random Access Read and Write Inputs/Outputs CE CMD ...
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... IDT70824S/L High-Speed Sequential Access Random Access Memory Truth Table: Sequential Address Pointer Operations Inputs/Outputs SLD SSTRT SSTRT SCLK 1 1 ↑ ↑ ↑ NOTES Don't Care, and High-Z = High-impedance RST is continuously HIGH. The conditions of SCE CNTEN, and SR/W are unrelated to the sequential address pointer operations. ...
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... IDT70824S/L High-Speed Sequential Access Random Access Memory Reset (RST) Setting RST LOW resets the control state of the SARAM. RST functions asynchronously of SCLK (i.e. not registered). The default states after a reset operation are displayed in the adjacent chart. Buffer Command Mode (CMD) Buffer Command Mode (CMD) allows the random access port to control the state of the two buffers ...
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... IDT70824S/L High-Speed Sequential Access Random Access Memory Flow Control Register Description 15 MSB NOTES: 1. "H" for I/O in the output state and "Don't Cares"' for I/O in the input state Writing a 0 into bit 4 releases the address pointer after it is stopped due to the STOP mode and allows sequential write operations to resume. This occurs asynchronously of SCLK, and therefore caution should be taken ...
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... IDT70824S/L High-Speed Sequential Access Random Access Memory Random Access Port: AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter READ CYCLE t Read Cycle Time RC t Address Access Time AA t Chip Enable Access Time ACE t Byte Enable Access Time ...
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... IDT70824S/L High-Speed Sequential Access Random Access Memory Waveform of Read Cycles: Random Access Port ADDR CLZ LB BLZ OE I/O OUT NOTES: 1. R/W is HIGH for read cycle. 2. Address valid prior to or coincident with CE transition LOW; otherwise t Waveform of Read Cycles: Buffer Command Mode ...
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... IDT70824S/L High-Speed Sequential Access Random Access Memory Waveform of Write Cycle No.1 (R/W Controlled Timing) Random Access Port (1,6) ADDR R (8) CE, LB, UB (5) I I/O OUT Waveform of Write Cycle No.2 (CE, LB, and/or UB Controlled Timing) Random Access Port (1,6,7) ADDR (8) CE, LB R/W I/O IN NOTES: 1. R/W, CE and UB must be inactive during all address transitions. ...
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... IDT70824S/L High-Speed Sequential Access Random Access Memory Sequential Port: AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter READ CYCLE t Sequential Clock Cycle Time CYC t Clock Pulse HIGH CH t Clock Pulse LOW CL t Count Enab le and Address Pointer Set-up Time ...
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... IDT70824S/L High-Speed Sequential Access Random Access Memory Sequential Port: AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Symbol Parameter WRITE CYCLE t Reset Pulse Width RSPW t Write Enable HIGH to Reset HIGH WERS t Reset HIGH to Write Enable LOW RSRC t Re set HIGH to Flag Valid ...
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... IDT70824S/L High-Speed Sequential Access Random Access Memory Sequential Port: Write, Pointer Load, Burst Read t CYC SCLK CNTEN t ES SLD SCE SOE SI/O OUT NOTES SLD = V , then address will be clocked in on the SCLK's rising edge. ...
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... IDT70824S/L High-Speed Sequential Access Random Access Memory Waveform of Write Cycles: Sequential Port t CYC SCLK CNTEN t ES SLD SI SR SCE SOE SI/O OUT Waveform of Burst Write Cycles: Sequential Port t CYC SCLK CNTEN t ES ...
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... IDT70824S/L High-Speed Sequential Access Random Access Memory Waveform of Write Cycles: Sequential Port (STRT/EOB Flag Timing SCLK CNTEN t ES SSTRT 1 SCE (3) SOE HIGH IMPEDANCE SI/O OUT EOB 1/2 NOTES: (Also used in Figure "Read STRT/EOB Flag Timing") 1 ...
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... IDT70824S/L High-Speed Sequential Access Random Access Memory Sequential Counter Enable Cycle After Reset, Write Cycle SCLK RST CNTEN (2) D0 SI/O IN Sequential Counter Enable Cycle After Reset, Read Cycle SCLK RST (3) SR/W (5) CNTEN SI/O OUT NOTES: 1. 'D0' represents data input for Address = 0, 'D1' represents data input for Address = 1, etc. ...
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... IDT70824S/L High-Speed Sequential Access Random Access Memory Random Access Port - Reset Timing RST R/W, SR/W CMD (4) or (UB + LB) EOB Flag Valid ( Random Access Port Restart Timing of Sequential Port SCLK R/W (2) (3) CLR Block (Internal Signal) NOTES: 1. The sequential port is in the STOP mode and is being restarted from the random port by the Bit 4 Counter Release (see Case 5). ...
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... IDT70824S/L High-Speed Sequential Access Random Access Memory Ordering Information IDT 70824 X XX Device Power Speed Type NOTE: 1. Industrial temperature range is available on selected TQFP packages in standard power. For specific speeds, packages and powers contact your sales office. Datasheet Document History 3/8/99: Initiated datasheet document history ...