MPC8248 Freescale Semiconductor, Inc, MPC8248 Datasheet
MPC8248
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MPC8248 Summary of contents
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... This hardware specification contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC8272 family of devices—the MPC8272, the MPC8248, the MPC8271, and the MPC8247. These devices are .13µm (HiP7) members of the PowerQUICC II™ family of integrated communications processors. They include on a single chip a 32-bit ™ ...
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... MPC8247VR MPC8271 MPC8247 516 PBGA Yes Yes Yes Yes Yes Yes — — — — — — Yes — — ZQ (516 PBGA—Lead spheres) MPC8272ZQ MPC8248ZQ MPC8271ZQ MPC8247ZQ Freescale Semiconductor ...
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Figure 1 shows the block diagram of the MPC8272. G2_LE Core Communication Processor Module (CPM Timers Interrupt Instruction Controller RAM Parallel I/O 32-bit RISC Microcontroller and Program ROM Baud Rate Generators FCC1 FCC2 SCC1 2 TDM Ports 1.1 ...
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Overview — Floating-point unit (FPU) supports floating-point arithmetic — Support for cache locking • Low-power consumption • Separate power supply for internal logic (1.5 V) and for I/O (3.3 V) • Separate PLLs for G2_LE core and for the communications ...
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... Integrated security engine (SEC) (MPC8272 and MPC8248 only) — Supports DES, 3DES, MD-5, SHA-1, AES, PKEU, RNG and RC-4 encryption algorithms in hardware • Communications processor module (CPM) — Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support for communications peripherals — Interfaces to G2_LE core through on-chip dual-port RAM and DMA controller. (Dual-port RAM size is 16 Kbyte plus 4Kbyte dedicated instruction RAM.) • ...
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Overview – Ethernet/IEEE 802.3 CDMA/CS – HDLC/SDLC and HDLC bus – Universal asynchronous receiver transmitter (UART) – Synchronous UART – Binary synchronous (BiSync) communications – Transparent – QUICC multichannel controller (QMC channels • Independent transmit and receive ...
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PCI-to-60x – PCI-to-60x to PCI-to-60x – 60x-to-PCI to 60x-to-PCI — Includes the configuration registers required by the PCI standard (which are automatically loaded from the EPROM to configure the MPC8272) and message and doorbell registers — Supports ...
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DC Electrical Characteristics Table 4. Recommended Operating Conditions Rating Junction temperature (maximum) Ambient temperature 1 Caution: These are the recommended and tested operating conditions. Proper operation outside of these conditions is not guaranteed. 2 Note that for extended temperature parts ...
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Table 5. DC Electrical Characteristics Characteristic Signal high input current 2 Output high voltage – except UTOPIA mode, and open drain pins 5 In UTOPIA mode (UTOPIA pins only): I PA[8–31] PB[18–31] ...
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DC Electrical Characteristics Table 5. DC Electrical Characteristics Characteristic I = 5.3mA OL CS[0-5] CS6/BCTL1/SMI CS7/TLBSYNC BADDR27/ IRQ1 BADDR28/ IRQ2 ALE/ IRQ4 BCTL0 PWE[0–7]/PSDDQM[0–7]/PBS[0–7] PSDA10/PGPL0 PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4 PSDAMUX/PGPL5 PCI_CFG0 (PCI_HOST_EN) PCI_CFG1 (PCI_ARB_EN) PCI_CFG2 (DLL_ENABLE) MODCK1/RSRV/TC(0)/BNKSEL(0) MODCK2/CSE0/TC(1)/BNKSEL(1) MODCK3/CSE1/TC(2)/BNKSEL(2) I ...
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The leakage current is measured for nominal VDDH,VCCSYN, and VDD. 5 MPC8272 and MPC8271 only. 4 Thermal Characteristics Table 6 describes thermal characteristics. Refer to Discussions of each characteristic are provided in sections 4.1 through 4.7. For the these ...
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Thermal Characteristics 4.2 Estimation with Junction-to-Case Thermal Resistance Historically, the thermal resistance has frequently been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance θJA θJC where junction-to-ambient ...
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Estimation Using Simulation When the board temperature is not known, a thermal simulation of the application is needed. The simple two-resistor model can be used with the thermal simulation of the application more accurate and complex model ...
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Power Dissipation 4.7 References Semiconductor Equipment and Materials International 805 East Middlefield Rd. Mountain View, CA 94043 MIL-SPEC and EIA/JESD (JEDEC) Specifications (Available from Global Engineering Documents) JEDEC Specifications 1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a ...
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AC Electrical Characteristics The following sections include illustrations and tables of clock diagrams, signals, and CPM outputs and inputs for 66.67-/83.33-/100-/133-MHz MPC8272 devices. Note that AC timings are based on a 50-pf load for MAX Delay and 10-pf load ...
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AC Electrical Characteristics Table 10 lists CPM input characteristics recommended that the rise/fall time on CPM input pins should not exceed 5 ns. This should be enforced especially on clock signals. Rise time refers to signal transitions from ...
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Figure 4 shows the FCC external clock. Serial ClKin sp16b FCC input signals FCC output signals Note: When GFMR[TCI FCC output signals Note: When GFMR[TCI Figure 5 shows the SCC/SMC/SPI/I Serial CLKin SCC/SMC/SPI/I2C input signals (See ...
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AC Electrical Characteristics Figure 6 shows the SCC/SMC/SPI/I BRG_OUT SCC/SMC/SPI/I2C input signals (See note) SCC/SMC/SPI/I2C output signals (See note) Note: There are four possible timing conditions for SCC and SPI: 1. Input sampled on the rising edge and output driven ...
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Figure 8 shows PIO and timer signals. PIO/IDMA/TIMER[TGATE assertion] input signals TIMER input signal [TGATE deassertion] IDMA output signals TIMER(sp42/43)/ PIO(sp42a/sp43a) Note: TGATE is asserted on the rising edge of the clock deasserted on the falling edge. 6.2 ...
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AC Electrical Characteristics The following conditions must be met in order to operate the MPC8272 family devices with 133 MHz bus: single PowerQUICC II Bus mode must be used (no external master, BCR[EBM] = 0); data bus must be in ...
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Activating data pipelining (setting BRx[DR] in the memory controller) improves the AC timing. Figure 9 shows the interaction of several bus signals. CLKin AACK/TA/TS/ DBG/BG/BR input signals ARTRY/TEA input signals DATA bus normal mode input signal All other input signals ...
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AC Electrical Characteristics Figure 10 shows signal behavior in MEMC mode. CLKin V_CLK Memory controller signals Generally, all MPC8272 bus and system output signals are driven from the rising edge of the input clock (CLKin). Memory controller signals, however, trigger ...
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The UPM machine outputs change on the internal tick determined by the memory controller programming; the AC specifications are relative to the internal tick. Note that SDRAM and GPCM machine outputs change on CLKin’s rising edge. 6.3 JTAG Timings Table ...
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Clock Configuration Modes Parameter JTAG external clock to output high impedance 1 All outputs are measured from the midpoint voltage of the falling/rising edge question. The output timings are measured at the pins. All output timings assume ...
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Both the PLLs and the dividers are set according to the selected clock operation mode as described in the following sections. Clock configurations change only after PORESET is asserted. The minimum Tval = 2 ns when ...
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Clock Configuration Modes Table 16. Clock Configurations for PCI Host Mode (PCI_MODCK=0) Bus Clock 3 Mode (MHz) Multiplication MODCK_H- Low High MODCK[1-3] 0010_011 50.0 66.7 0010_100 75.0 100.0 0010_101 75.0 100.0 0010_110 75.0 100.0 0011_000 50.0 66.7 0011_001 50.0 66.7 ...
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Table 16. Clock Configurations for PCI Host Mode (PCI_MODCK=0) Bus Clock 3 Mode (MHz) Multiplication MODCK_H- Low High MODCK[1-3] 0110_100 60.0 80.0 0110_101 60.0 80.0 0110_110 60.0 80.0 0111_000 0111_001 50.0 66.7 0111_010 50.0 66.7 0111_011 50.0 66.7 0111_100 50.0 ...
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Clock Configuration Modes Table 16. Clock Configurations for PCI Host Mode (PCI_MODCK=0) Bus Clock 3 Mode (MHz) Multiplication MODCK_H- Low High MODCK[1-3] 1010_010 75.0 100.0 1010_011 75.0 100.0 1010_100 75.0 100.0 1010_101 100.0 133.3 1010_110 100.0 133.3 1010_111 100.0 133.3 ...
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Table 16. Clock Configurations for PCI Host Mode (PCI_MODCK=0) Bus Clock 3 Mode (MHz) Multiplication MODCK_H- Low High MODCK[1-3] 1100_000 1100_001 1100_010 1 The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency ...
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Clock Configuration Modes Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=1) Bus Clock 3 Mode (MHz) Multiplication MODCK_H- Low High MODCK[1-3] 0010_000 50.0 100.0 0010_001 50.0 100.0 0010_010 50.0 100.0 0010_011 50.0 100.0 0010_100 37.5 75.0 0010_101 37.5 75.0 ...
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Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=1) Bus Clock 3 Mode (MHz) Multiplication MODCK_H- Low High MODCK[1-3] 0110_001 60.0 120.0 0110_010 60.0 120.0 0110_011 60.0 120.0 0110_100 60.0 120.0 0110_101 60.0 120.0 0110_110 60.0 120.0 0111_000 0111_001 50.0 ...
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Clock Configuration Modes Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=1) Bus Clock 3 Mode (MHz) Multiplication MODCK_H- Low High MODCK[1-3] 1010_000 75.0 150.0 1010_001 75.0 150.0 1010_010 75.0 150.0 1010_011 75.0 150.0 1010_100 75.0 150.0 1010_101 100.0 200.0 ...
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Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=1) Bus Clock 3 Mode (MHz) Multiplication MODCK_H- Low High MODCK[1-3] 1110_100 50.0 100.0 1100_000 1100_001 1100_010 1 The “low” values are the minimum allowable frequencies for a given clock mode. The ...
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Clock Configuration Modes Table 18. Clock Configurations for PCI Agent Mode (PCI_MODCK=0) PCI Clock 3 Mode (MHz) Multiplication MODCK_H- Low High MODCK[1-3] 0000_111 50.0 66.7 0001_001 60.0 66.7 0001_010 50.0 66.7 0001_011 50.0 66.7 0001_100 50.0 66.7 0010_001 50.0 66.7 ...
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Table 18. Clock Configurations for PCI Agent Mode (PCI_MODCK=0) PCI Clock 3 Mode (MHz) Multiplication MODCK_H- Low High MODCK[1-3] 0101_110 50.0 66.7 0110_000 0110_001 50.0 66.7 0110_010 50.0 66.7 0110_011 50.0 66.7 0110_100 50.0 66.7 0111_000 50.0 66.7 0111_001 50.0 ...
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Clock Configuration Modes Table 18. Clock Configurations for PCI Agent Mode (PCI_MODCK=0) PCI Clock 3 Mode (MHz) Multiplication MODCK_H- Low High MODCK[1-3] 1010_100 50.0 66.7 1011_000 1011_001 50.0 66.7 1011_010 50.0 66.7 1011_011 50.0 66.7 1011_100 50.0 66.7 1011_101 50.0 ...
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Table 18. Clock Configurations for PCI Agent Mode (PCI_MODCK=0) PCI Clock 3 Mode (MHz) Multiplication MODCK_H- Low High MODCK[1-3] 1110_111 50.0 66.7 1100_000 1100_001 1100_010 1 The “low” values are the minimum allowable frequencies for a given clock mode. The ...
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Clock Configuration Modes Table 19. Clock Configurations for PCI Agent Mode (PCI_MODCK=1) PCI Clock 3 Mode (MHz) Multiplication MODCK_H- Low High MODCK[1-3] 0001_100 25.0 50.0 0010_001 25.0 50.0 0010_010 25.0 50.0 0010_011 25.0 50.0 0010_100 25.0 50.0 0011_000 0011_001 37.5 ...
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Table 19. Clock Configurations for PCI Agent Mode (PCI_MODCK=1) PCI Clock 3 Mode (MHz) Multiplication MODCK_H- Low High MODCK[1-3] 0110_011 25.0 50.0 0110_100 25.0 50.0 0111_000 25.0 50.0 0111_001 25.0 50.0 0111_010 25.0 50.0 0111_011 25.0 50.0 1000_000 1000_001 25.0 ...
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Clock Configuration Modes Table 19. Clock Configurations for PCI Agent Mode (PCI_MODCK=1) PCI Clock 3 Mode (MHz) Multiplication MODCK_H- Low High MODCK[1-3] 1011_011 25.0 50.0 1011_100 25.0 50.0 1011_101 25.0 50.0 1011_110 25.0 50.0 1011_111 25.0 50.0 1100_101 25.0 50.0 ...
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The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a table entry guarantees only the required minimum CPU operating frequency. The “high” values are for the purpose of illustration only. ...
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... Not to Scale Figure 12. Pinout of the 516 PBGA Package (View from Top) Table 20 shows the pinout of the MPC8272. Note that the pins in the ‘MPC8272/8271 only” column relate to Utopia functionality. MPC8272/MPC8248 and MPC8271/MPC8247 BR BG/IRQ6 ABB/IRQ2 TS MPC8272 PowerQUICC II™ ...
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... MPC8272/MPC8248 and MPC8271/MPC8247 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 1.5 Freescale Semiconductor Table 20. Pinout (continued) ...
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... Pinout MPC8272/MPC8248 and MPC8271/MPC8247 A31 TT0 TT1 TT2 TT3 TT4 TBST TSIZ0 TSIZ1 TSIZ2 TSIZ3 AACK ARTRY DBG/IRQ7 DBB/IRQ3 D10 D11 D12 D13 D14 D15 MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 1.5 44 Table 20. Pinout (continued) Pin Name ...
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... MPC8272/MPC8248 and MPC8271/MPC8247 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 1.5 Freescale Semiconductor Table 20 ...
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... Pinout MPC8272/MPC8248 and MPC8271/MPC8247 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 IRQ3/CKSTP_OUT/EXT_BR3 IRQ4/CORE_SRESET/EXT_BG3 IRQ5/TBEN/EXT_DBG3/CINT PSDVAL TA TEA GBL/IRQ1 CI/BADDR29/IRQ2 WT/BADDR30/IRQ3 BADDR31/IRQ5/CINT CPU_BR/INT_OUT CS0 CS1 CS2 MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 1.5 46 Table 20 ...
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... MPC8272/MPC8248 and MPC8271/MPC8247 CS3 CS4 CS5 CS6/BCTL1/SMI CS7/TLBISYNC BADDR27/IRQ1 BADDR28/IRQ2 ALE/IRQ4 BCTL0 PWE0/PSDDQM0/PBS0 PWE1/PSDDQM1/PBS1 PWE2/PSDDQM2/PBS2 PWE3/PSDDQM3/PBS3 PWE4/PSDDQM4/PBS4 PWE5/PSDDQM5/PBS5 PWE6/PSDDQM6/PBS6 PWE7/PSDDQM7/PBS7 PSDA10/PGPL0 PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4 PSDAMUX/PGPL5 1 PCI_MODE PCI_CFG0 (PCI_HOST_EN) PCI_CFG1 (PCI_ARB_EN) PCI_CFG2 (DLL_ENABLE) PCI_ PAR PCI_FRAME PCI_TRDY PCI_IRDY MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 1.5 Freescale Semiconductor Table 20 ...
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... Pinout MPC8272/MPC8248 and MPC8271/MPC8247 PCI_STOP PCI_DEVSEL PCI_IDSEL PCI_PERR PCI_SERR PCI_REQ0 PCI_REQ1/CPCI_HS_ES PCI_GNT0 PCI_GNT1/CPCI_HS_LED PCI_GNT2/CPCI_HS_ENUM PCI_RST PCI_INTA PCI_REQ2 DLLOUT PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 1.5 48 Table 20 ...
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... MPC8272/MPC8248 and MPC8271/MPC8247 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_C0/BE0 PCI_C1/BE1 PCI_C2/BE2 PCI_C3/BE3 IRQ0/NMI_OUT 2 TRST TCK TMS TDI TDO TRIS 2 PORESET /PCI_RST HRESET SRESET RSTCONF MODCK1/RSRV/TC0/BNKSEL0 MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 1.5 Freescale Semiconductor Table 20 ...
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... Pinout MPC8272/MPC8248 and MPC8271/MPC8247 MODCK2/CSE0/TC1/BNKSEL1 MODCK3/CSE1/TC2/BNKSEL2 CLKIN1 PA8/SMRXD2 PA9/SMTXD2 PA10/MSNUM5 PA11/MSNUM4 PA12/MSNUM3 PA13/MSNUM2 PA14/FCC1_MII_HDLC_RXD3 PA15/FCC1_MII_HDLC_RXD2 PA16/FCC1_MII_HDLC_RXD1 PA17/FCC1_MII_HDLC_RXD0/ FCC1_MII_TRAN_RXD/FCC1_RMII_RX D0 PA18/FCC1_MII_HDLC_TXD0/FCC1_M II_TRAN_TXD/ FCC1_RMII_TXD0 PA19/FCC1_MII_HDLC_TXD1/FCC1_R MII_TXD1 PA20/FCC1_MII_HDLC_TXD2 PA21/FCC1_MII_HDLC_TXD3 PA22 PA23 PA24/MSNUM1 PA25/MSNUM0 PA26/FCC1_MII_RMIIRX_ER PA27/FCC1_MII_RX_DV/FCC1_RMII_C RS_DV PA28/FCC1_MII_RMII_TX_EN PA29/FCC1_MII_TX_ER PA30/FCC1_MII_CRS/FCC1_RTS PA31/FCC1_MII_COL MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 1.5 50 Table 20 ...
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... MPC8272/MPC8248 and MPC8271/MPC8247 PB18/FCC2_MII_HDLC_RXD3 PB19/FCC2_MII_HDLC_RXD2 PB20/FCC2_MII_HDLC_RMII_RXD1 PB21/FCC2_MII_HDLC_RMII_RXD0/FCC2_TRAN_RXD PB22/FCC2_MII_HDLC_TXD0/FCC2_TRAN_TXD/ FCC2_RMII_TXD0 PB23/FCC2_MII_HDLC_TXD1/FCC2_RMII_TXD1 PB24/FCC2_MII_HDLC_TXD2/L1RSYNCB2 PB25/FCC2_MII_HDLC_TXD3/L1TSYNCB2 PB26/FCC2_MII_CRS/L1RXDB2 PB27/FCC2_MII_COL/L1TXDB2 PB28/FCC2_MII_RMII_RX_ER/FCC2_RTS/TXD1 PB29/FCC2_MII_RMII_TX_EN PB30/FCC2_MII_RX_DV/FCC2_RMII_CRS_DV PB31/FCC2_MII_TX_ER PC0/DREQ3/BRGO7/SMSYN1/L1CLKOA2 PC1/BRGO6/L1RQA2 PC4/SMRXD1/SI2_L1ST4/FCC2_CD PC5/SMTXD1/SI2_L1ST3/FCC2_CTS PC6/FCC1_CD/SI2_L1ST2 PC7/FCC1_CTS PC8/CD4/RTS1/SI2_L1ST2/CTS3 PC9/CTS4/L1TSYNCA2 PC10/CD3/USB_RN PC11/CTS3/USB_RP/L1TXD3A2 PC12 PC13/BRGO5 PC14/CD1 PC15/CTS1 PC16/CLK16 PC17/CLK15/BRGO8/DONE2 MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 1.5 Freescale Semiconductor Table 20 ...
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... Pinout MPC8272/MPC8248 and MPC8271/MPC8247 PC18/CLK14/TGATE2 PC19/CLK13/BRGO7/TGATE1 PC20/CLK12/USBOE PC21/CLK11/BRGO6/CP_INT PC22/CLK10/DONE3 PC23/CLK9/BRGO5/DACK3/CD1 PC24/CLK8/TIN3/TOUT4/DREQ2/BRGO1 PC25/CLK7/BRGO4/DACK2/SPISEL PC26/CLK6/TOUT3/TMCLK PC27/CLK5/BRGO3/TOUT1 PC28/CLK4/TIN1/TOUT2/SPICLK PC29/CLK3/TIN2/BRGO2/CTS1 PD7/SMSYN2 PD14/I2CSCL PD15/I2CSDA PD16/SPIMISO PD17/BRGO2/SPIMOSI PD18/SPICLK PD19/SPISEL/BRGO1 PD20/RTS4/L1RSYNCA2 PD21/TXD4/L1RXD0A2 PD22/RXD4/L1TXD0A2 PD23/RTS3/USB_TP PD24/TXD3/USB_TN PD25/RXD3/USB_RXD PD29/RTS1 PD30/TXD1 PD31/RXD1 VCCSYN VCCSYN1 CLKIN2 MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 1.5 52 Table 20 ...
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... MPC8272/MPC8248 and MPC8271/MPC8247 4 No connect I/O power Core Power Ground 1 Must be tied to ground. 2 Should be tied to VDDH via a 2K Ω external pull-up resistor. 3 The default configuration of the CPM pins (PA[8–31], PB[18–31], PC[0–1,4–29], PD[7–25, 29–31]) is input. To prevent excessive DC current recommended either to pull unused pins to GND or VDDH configure them as outputs. ...
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Package 9 Package Figure 13 shows the side profile of the PBGA package. Transfer molding compound Plated substrate via 1 mm pitch Figure 13. Side View of the PBGA Package Remove Table 21 provides package parameters. nomenclature of the 516 ...
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Figure 14. Mechanical Dimensions and Bottom Surface Nomenclature—516 PBGA MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 1.5 Freescale Semiconductor Package 55 ...
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Ordering Information 10 Ordering Information Figure 15 provides an example of the Freescale part numbering nomenclature for the MPC8272. In addition to the processor frequency, the part numbering scheme also consists of a part modifier that indicates any enhancement(s) in ...
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Document Revision History Table 22 lists significant changes between revisions of this hardware specification. Date Revision 1.5 12/2006 • Section 6, “AC Electrical Characteristics,” timing descriptions. 1.4 05/2006 • Added row for 133 MHz configurations to 1.3 02/2006 • ...
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Document Revision History Table 22. Document Revision History (continued) Date Revision 0.2 12/2003 • Table 1: New • Table 2: New • Table 4: Modification of VDD and VCCSYN to 1.45–1.60 V • Table 5: Addition of note 2 regarding ...
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THIS PAGE INTENTIONALLY LEFT BLANK MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 1.5 Freescale Semiconductor Document Revision History 59 ...
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... Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power ...