P87LPC764 NXP Semiconductors, P87LPC764 Datasheet
P87LPC764
Available stocks
Related parts for P87LPC764
P87LPC764 Summary of contents
Page 1
... P87LPC764 Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP Product data Supersedes data of 2001 Oct 26 hilips Semiconductors INTEGRATED CIRCUITS 2003 Sep 03 ...
Page 2
... The P87LPC764 is a 20-pin single-chip microcontroller designed for low pin count applications demanding high-integration, low cost solutions over a wide range of performance requirements. A member of the Philips low pin count family, the P87LPC764 offers programmable oscillator configurations for high and low speed crystals or RC operation, wide operating voltage range, programmable port output configurations, selectable Schmitt trigger inputs, LED drive outputs, and a built-in watchdog timer ...
Page 3
... DEVICE COMPARISON TABLE Part type P87LPC764BD/01, BDH/01 P87LPC764BDH, HDH P87LPC764BD, BN, FN, FD, FDH NOTE: 1. Please see AC and DC characteristics for more details. PIN CONFIGURATION, 20-PIN DIP, SO, AND TSSOP PACKAGES 2003 Sep 03 Frequency 20 MHz (5 V), ...
Page 4
... Philips Semiconductors Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP LOGIC SYMBOL CMP2 CIN2B CIN2A CIN1B CIN1A CMPREF CMP1 T1 CLKOUT/X2 X1 2003 Sep TxD RxD T0 INT0 INT1 RST 3 Product data P87LPC764 SCL SDA SU01150 ...
Page 5
... PORT 2 CONFIGURABLE I/OS PORT 1 CONFIGURABLE I/OS PORT 0 CONFIGURABLE I/OS KEYPAD INTERRUPT CONFIGURABLE CRYSTAL OR OSCILLATOR RESONATOR 2003 Sep 03 ACCELERATED 80C51 CPU INTERNAL BUS TIMER 0, 1 WATCHDOG TIMER AND OSCILLATOR ANALOG COMPARATORS POWER MONITOR (POWER-ON RESET, BROWNOUT RESET) ON-CHIP RC OSCILLATOR 4 Product data P87LPC764 UART SU01151 ...
Page 6
... MEMORY SPACE * The 87LPC764 does not support access to external data memory. However, the User Configuration Bytes are accessed via the MOVX instruction as if they were in external data memory. Figure 1. P87LPC764 Program and Data Memory Map 2003 Sep 03 FFh SPECIAL FUNCTION REGISTERS ...
Page 7
... EPROM configuration). CLKOUT CPU clock divided by 6 clock output when enabled via SFR bit and in conjunction with internal RC oscillator or external clock input. X1 Input to the oscillator circuit and internal clock generator circuits (when selected via the EPROM configuration). 6 Product data P87LPC764 ...
Page 8
... A4h P2S P1S P0S ENCLK A5h – – – – 87h SMOD1 SMOD0 BOF POF 7 Product data P87LPC764 Reset Value LSB 00h 1 SRST 0 – DPS 02h 00h 1 CN1 OE1 CO1 ...
Page 9
... TF1 TR1 TF0 TR0 8Ch 8Dh 8Ah 8Bh 89h GATE C A7h – – WDOVF WDRUN A6h 8 Product data P87LPC764 Reset Value LSB RS0 00h 00h TB8 RB8 TI RI 00h xxh 00h 00h ...
Page 10
... The P87LPC764 uses an enhanced 80C51 CPU which runs at twice the speed of standard 80C51 devices. This means that the performance of the P87LPC764 running at 5 MHz is exactly the same as that of a standard 80C51 running at 10 MHz. A machine cycle consists of 6 oscillator cycles, and most instructions execute clocks ...
Page 11
... COn CMPREF CINnA COn V (1.23V) ref CINnB COn CMPREF CINnB COn V (1.23V) ref Figure 4. Comparator Configurations 10 Product data P87LPC764 CMP1 (P0.6) CMF1 INTERRUPT CMP2 (P0.0) CMF2 INTERRUPT SU01153 CPn, CNn, OEn = COn CMPn – CPn, CNn, OEn = COn CMPn – CPn, CNn, OEn = ...
Page 12
... Output to CMP1 pin enabled. ; The comparator has to start up for at ; least 10 microseconds before use. ; Clear comparator 1 interrupt flag. ; Enable the comparator 1 interrupt. The ; priority is left at the current value. ; Enable the interrupt system (if needed). ; Return to caller. Figure 5. 11 Product data P87LPC764 SU01189 ...
Page 13
... The first five of these times are 4.7 ms (see I are covered by the low order three bits of timer I. Timer I is clocked by the P87LPC764 CPU clock. Timer I can be pre-loaded with one of four values to optimize timing for different oscillator frequencies. At lower frequencies, software response time is increased and will degrade maximum performance of the I register I2CFG description for prescale values (CT0, CT1) ...
Page 14
... STR, or STP is set, clearing DRDY will not release SCL to high that the I C will not the next bit program detects ATN = 1, and DRDY = 0, it should examine ARL, STR, and STP. 13 Product data P87LPC764 Reset Value: 81h 1 0 — XSTR XSTP 2 ...
Page 15
... XDAT = 0; it sets Transmit Active and drives SDA low during the SCL low time. After SCL goes high, the I hardware waits for the suitable minimum time and then releases SDA to high to make the stop condition. 14 Product data P87LPC764 2 C interface will only drive 2 C hardware to 2 ...
Page 16
... SCL when this device is a master on the I controls both of these parameters, and also the timing for stop and start conditions. Regarding Software Response Time Because the P87LPC764 can run at 20 MHz, and because the I interface is optimized for high-speed operation quite likely that 2 ...
Page 17
... Interrupts The P87LPC764 uses a four priority level interrupt structure. This allows great flexibility in controlling the handling of the P87LPC764’s many interrupt sources. The P87LPC764 supports interrupt sources. Each interrupt source can be individually enabled or disabled by setting or clearing a bit in registers IEN0 or IEN1. The IEN0 register also contains a global disable bit, EA, which disables all interrupts at once ...
Page 18
... IEn when the interrupt is level sensitive, it simply tracks the input pin level external interrupt is enabled when the P87LPC764 is put into Power Down or Idle mode, the interrupt will cause the processor to wake up and resume operation. Refer to the section on Power Reduction Modes for details ...
Page 19
... Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP I/O Ports18 The P87LPC764 has 3 I/O ports, port 0, port 1, and port 2. The exact number of I/O pins available depend upon the oscillator and reset options chosen. At least 15 pins of the P87LPC764 may be used as I/Os when a two-pin external oscillator and an external reset circuit are used ...
Page 20
... The last two functions are described in the Timer/Counters and Oscillator sections respectively. The enable bits for all of these functions are shown in Figure 13. Each I/O port of the P87LPC764 may be selected to use TTL level inputs or Schmitt inputs with hysteresis. A single configuration bit determines this selection for the entire port. Port pins P1.2, P1.3, and P1 ...
Page 21
... CPU from Idle or Power Down modes. This feature is particularly useful in handheld, battery powered systems that need to carefully manage power consumption yet also need to be convenient to use. The P87LPC764 allows any or all pins of port enabled to cause this interrupt. Port pins are enabled by the setting of bits in 2003 Sep 03 ...
Page 22
... Note: the Keyboard Interrupt must be enabled in order for the settings of the KBI register to be effective. The interrupt flag (KBF) is located at bit 7 of AUXR1. 2003 Sep 03 EKB (FROM IEN1 REGISTER) Figure 14. Keyboard Interrupt KBI.5 KBI.4 KBI.3 KBI.2 KBI.1 Figure 15. Keyboard Interrupt Register (KBI) 21 Product data P87LPC764 KBF (KBI INTERRUPT) SU01163 Reset Value: 00h 1 0 KBI.0 SU01164 ...
Page 23
... Clock Output The P87LPC764 supports a clock output function when either the on-chip RC oscillator or external clock input options are selected. This allows external devices to synchronize to the P87LPC764. When enabled, via the ENCLK bit in the P2M1 register, the clock output appears on the X2/CLKOUT pin whenever the on-chip oscillator is running, including in Idle mode ...
Page 24
... A CLOCK OUTPUT MAY BE OBTAINED ON THE X2 PIN BY SETTING THE ENCLK BIT IN THE P2M1 REGISTER. 2003 Sep 03 QUARTZ CRYSTAL OR CERAMIC RESONATOR Figure 16. Using the Crystal Oscillator CMOS COMPATIBLE EXTERNAL OSCILLATOR SIGNAL Figure 17. Using an External Clock Input 23 Product data P87LPC764 87LPC764 SU01165 87LPC764 X1 X2 SU01166 ...
Page 25
... P87LPC764 instruction and peripheral timing to match standard 80C51 timing by dividing the CPU clock by two. Default timing for the P87LPC764 is 6 CPU clocks per machine cycle while standard 80C51 timing is 12 clocks per machine cycle. This division also applies to peripheral timing, allowing 80C51 code that is oscillator frequency and/or timer rate dependent ...
Page 26
... When this feature is activated, the POF flag in the PCON register is set to indicate an initial power up condition. The POF flag will remain set until cleared by software. Power Reduction Modes The P87LPC764 supports Idle and Power Down modes of power reduction. Idle Mode The Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated ...
Page 27
... Brownout Detect Interrupt The BOD bit in AUXR1 must not be set (brownout detect not disabled). The BOI bit in AUXR1 must be set (brownout interrupt enabled). The corresponding interrupt must be enabled. Reset Input The external reset input must be enabled. 2003 Sep 03 26 Product data P87LPC764 ...
Page 28
... While the signal on the RST pin is less than low, the P87LPC764 is held in reset until the signal goes high. The watchdog timer on the LPC764 can act as an oscillator fail detect because it uses an independent, fully on-chip oscillator. UCFG1 is described in the System Configuration Bytes section of this datasheet ...
Page 29
... Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP Timer/Counters The P87LPC764 has two general purpose counter/timers which are upward compatible with the standard 80C51 Timer 0 and Timer 1. Both can be configured to operate either as timers or event counters (see Figure 22). An option to automatically toggle the T0 and/or T1 pins upon timer overflow has been added. In the “ ...
Page 30
... Figure 24. There are two different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3 TF0 TR0 IE1 IT1 IE0 TLn THn (5 BITS) (8 BITS) CONTROL TOGGLE 29 Product data P87LPC764 Reset Value: 00h 0 IT0 SU01172 OVERFLOW TFn INTERRUPT Tn PIN TnOE SU01173 ...
Page 31
... TH0 now controls the “Timer 1” interrupt. Mode 3 is provided for applications that require an extra 8-bit timer. With Timer 0 in Mode 3, an P87LPC764 can look like it has three Timer/Counters. When Timer Mode 3, Timer 1 can be turned on and off by switching it into and out of its own Mode 3. It can still be used by the serial port as a baud rate generator any application not requiring an interrupt ...
Page 32
... The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on. UART The P87LPC764 includes an enhanced 80C51 UART. The baud rate source for the UART is timer 1 for modes 1 and 3, while the rate is fixed in modes 0 and 2. Because CPU clocking is different on the P87LPC764 than on the standard 80C51, baud rate calculation is somewhat different ...
Page 33
... SM2 REN TB8 RB8 Baud Rate CPU clock/6 Variable (see text) CPU clock/32 or CPU clock/16 Variable (see text) Figure 28. Serial Port Control Register (SCON) 32 Product data P87LPC764 Reset Value: 00h SU01157 ...
Page 34
... Product data P87LPC764 CPU clock frequency 192 ( SMOD1 + 1) 256 * (TH1) 38.4k 57.6k * 7.3728 * 11.0592 * 14.7456 – – – – – – – – – – ...
Page 35
... Product data P87LPC764 57.6k 115.2k 5.5296 * 11.0592 * 11.0592 – 16.5888 – – – – – – – – – – – – – ...
Page 36
... Ten bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. In the P87LPC764 the baud rate is determined by the Timer 1 overflow rate. Figure 30 shows a simplified functional diagram of the serial port in Mode 1, and associated timings for transmit receive ...
Page 37
... INTERNAL BUS S1 ... S6 S1 ... S6 S1 ... S6 S1 ... S6 S1 ... S6 S1 ... Figure 29. Serial Port Mode 0 36 Product data P87LPC764 RxD P1.1 ALT OUTPUT FUNCTION TxD P1.0 ALT OUTPUT FUNCTION SHIFT CLOCK RXD P1.1 ALT INPUT FUNCTION S1 ... S6 S1 ... S6 S1 ... S6 TRANSMIT D7 RECEIVE D6 ...
Page 38
... INPUT SHIFT REGISTER DETECTOR LOAD SBUF SBUF READ SBUF 80C51 INTERNAL BUS Figure 30. Serial Port Mode 1 37 Product data P87LPC764 TxD P1.0 ALT OUTPUT FUNCTION SERIAL PORT INTERRUPT TRANSMIT D6 D7 STOP BIT D6 D7 STOP BIT RECEIVE SU01179 ...
Page 39
... SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit, although this is better done with the Framing Error flag Mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. 38 Product data P87LPC764 ...
Page 40
... INPUT SHIFT REGISTER LOAD SBUF SBUF READ SBUF 80C51 INTERNAL BUS Figure 31. Serial Port Mode 2 39 Product data P87LPC764 TxD P1.0 ALT OUTPUT FUNCTION SERIAL PORT INTERRUPT TRANSMIT D6 D7 TB8 STOP BIT D6 D7 RB8 STOP BIT RECEIVE SU01180 ...
Page 41
... INPUT SHIFT REGISTER DETECTOR LOAD SBUF SBUF READ SBUF 80C51 INTERNAL BUS Figure 32. Serial Port Mode 3 40 Product data P87LPC764 TxD P1.0 ALT OUTPUT FUNCTION SERIAL PORT INTERRUPT TRANSMIT D6 D7 TB8 STOP BIT D6 D7 RB8 STOP BIT RECEIVE SU01181 ...
Page 42
... If the CPU clock was still running, code execution will begin immediately after that. If the processor was in Power Down mode, the watchdog reset will start the oscillator and code execution will resume after the oscillator is stable. 41 Product data P87LPC764 ...
Page 43
... Minimum Time Nominal Time 100 200 ms 165 ms 400 ms 330 ms 800 ms 660 ms 1.60 sec 1.3 sec 3.20 sec 42 Product data P87LPC764 WATCHDOG RESET WATCHDOG INTERRUPT WDTE (UCFG1.7) S WDOVF Q (WDCON.5) R SU01754 1 0 WDS0 Maximum Time 160 ms 320 ms 640 ms 1280 ms 2 ...
Page 44
... DPTR) will be affected by the setting of DPS. The MOVX instructions have limited application for the P87LPC764 since the part does not have an external data bus. However, they may be used to access EPROM configuration information (see EPROM Characteristics section). ...
Page 45
... UCFG bytes are programmed. System Configuration Bytes A number of user configurable features of the P87LPC764 must be defined at power up and therefore cannot be set by the program after start of execution. Those features are configured through the use of two EPROM bytes that are programmed in the same manner as the EPROM program space ...
Page 46
... Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 2003 Sep — — — — — Protection Description 45 Product data P87LPC764 Unprogrammed Value: FFh 0 — SU01186 RATING UNIT –55 to +125 C –65 to +150 +11.0 V –0 +0.5V ...
Page 47
... Philips Semiconductors Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP DC ELECTRICAL CHARACTERISTICS (FOR P87LPC764BD, BN, BDH, FN, FD, FDH, BD/01, BDH/01 2 6.0 V unless otherwise specified SYMBOL SYMBOL PARAMETER PARAMETER I I Power su Power supply current operating ly current, o erating DD DD ...
Page 48
... Philips Semiconductors Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP COMPARATOR ELECTRICAL CHARACTERISTICS (FOR P87LPC764BD, BN, BDH, FN, FD, FDH, BD/01, BDH/01 3 6.0 V unless otherwise specified SYMBOL SYMBOL PARAMETER PARAMETER V Offset voltage comparator inputs IO V Common mode range comparator inputs ...
Page 49
... Philips Semiconductors Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP AC ELECTRICAL CHARACTERISTICS (FOR P87LPC764BD, BDH, BN, FN, FD, FDH + – + amb DD SYMBOL SYMBOL FIGURE FIGURE External Clock f 39 Oscillator frequency (V osc f 39 Oscillator frequency (V ...
Page 50
... Philips Semiconductors Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP AC ELECTRICAL CHARACTERISTICS (FOR P87LPC764BD/01, BDH/ 6.0 V unless otherwise specified; V amb DD SYMBOL SYMBOL FIGURE FIGURE External Clock f 39 Oscillator frequency (V osc f 39 Oscillator frequency (V ...
Page 51
... Philips Semiconductors Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP DC ELECTRICAL CHARACTERISTICS (FOR P87LPC764HDH 4 5 – +125 C. DD amb SYMBOL SYMBOL PARAMETER PARAMETER I Power supply current, operating DD I Power supply current, Idle mode ID I Power supply current, Power Down mode ...
Page 52
... Philips Semiconductors Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP COMPARATOR ELECTRICAL CHARACTERISTICS (FOR P87LPC764HDH 4 5 – +125 C DD amb SYMBOL SYMBOL PARAMETER PARAMETER V Offset voltage comparator inputs IO V Common mode range comparator inputs CR 1 CMRR ...
Page 53
... Philips Semiconductors Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP AC ELECTRICAL CHARACTERISTICS (FOR P87LPC764HDH 4 5 – +125 C DD amb SYMBOL SYMBOL FIGURE FIGURE PARAMETER PARAMETER External Clock f 39 osc t 39 Clock period and CPU timing cycle ...
Page 54
... DD – 0 CHCL CLCX t C Figure 39. External Clock Timing 1000 6.0 V 5.0 V 100 4.0 V 3 100 100 SU01202 Figure 41. Typical Idd versus frequency (medium frequency 53 Product data P87LPC764 SET TI VALID VALID VALID SET RI SU01187 t CHCX t CLCH SU01188 6.0 V 6.0 V 5.0 V 5.0 V 4.0 V 3.3 V 2.7 V 2.7 V 1,000 ...
Page 55
... Figure 45. Typical Idle Idd versus frequency (external clock, 10,000 5.0 V 4.0 V 3.3 V 1,000 2.7 V 100 10 10,000 100,000 10 SU01205 Figure 46. Typical Idle Idd versus frequency (external clock, 4.0 V 3.3 V 2.7 V 10,000 SU01206 54 Product data P87LPC764 4.0 V 3.3 V 2.7 V 100 1,000 10,000 Frequency (kHz) SU01207 25 C, LPEP=1) 5.0 V 4.0 V 6.0 V 3.3 V 2.7 V 100 1,000 10,000 100,000 Frequency (kHz) SU01208 ...
Page 56
... Philips Semiconductors Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP DIP20: plastic dual in-line package; 20 leads (300 mil) 2003 Sep 03 55 Product data P87LPC764 SOT146-1 ...
Page 57
... Philips Semiconductors Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP SO20: plastic small outline package; 20 leads; body width 7.5 mm 2003 Sep 03 56 Product data P87LPC764 SOT163-1 ...
Page 58
... Philips Semiconductors Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm 2003 Sep 03 57 Product data P87LPC764 SOT360-1 ...
Page 59
... OTP REVISION HISTORY Rev Date Description _11 20030903 Product data (9397 750 11121); ECN 853-2401 30269 Modifications: Added BD/01, BDH/01 and HDH part types _10 20011026 Preliminary data (9397 750 09017); previous release 2003 Sep 03 58 Product data P87LPC764 ...
Page 60
... Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Fax: + 24825 Document order number: 59 Product data P87LPC764 2 C patent Koninklijke Philips Electronics N.V. 2003 All rights reserved. Printed in U.S.A. Date of release: 09-03 ...