pca9665 NXP Semiconductors, pca9665 Datasheet
pca9665
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pca9665 Summary of contents
Page 1
... Communication with the I carried out on a Byte or Buffered mode using interrupt or polled handshake. The PCA9665 controls all the I no external timing element required. The PCA9665 has the same footprint as the PCA9564 with additional features: • 1 MHz transmission speeds • ...
Page 2
... Type number Topside mark PCA9665BS 9665 PCA9665D PCA9665D PCA9665N PCA9665N PCA9665PW PCA9665 PCA9665_2 Product data sheet 2 C-bus port to controllers/processors that do not have one 2 C-bus ports to controllers/processors that need multiple I Package Name Description HVQFN20 plastic thermal enhanced very thin quad flat package; ...
Page 3
... NXP Semiconductors 5. Block diagram PCA9665 FILTER SDA SDA CONTROL AA ENSIO STA STO SI FILTER SCL SCL CONTROL ENSIO STA STO SI CLOCK SELECTOR OSCILLATOR Fig 1. Block diagram of PCA9665 PCA9665_2 Product data sheet data BUS BUFFER SD7 SD6 SD5 SD4 68-BYTE I2CDAT – data register – read/write BUFFER – ...
Page 4
... 002aab019 Rev. 02 — 7 December 2006 PCA9665 2 Fm+ parallel bus to I C-bus controller PCA9665PW i. 002aab021 Fig 3. Pin configuration of TSSOP20 terminal 1 index area PCA9665BS ...
Page 5
... I power Rev. 02 — 7 December 2006 PCA9665 Fm+ parallel bus to I Description Data bus: Bidirectional 3-state data bus used to transfer commands, data and status between the bus controller and the CPU the least significant bit. internally connected: must be left floating (pulled ...
Page 6
... I byte or buffered basis, using either an interrupt or polled handshake. 7.2 Internal oscillator The PCA9665 contains an internal 28.5 MHz oscillator which is used for all I The oscillator requires up to 550 s to start-up after ENSIO bit is set to ‘1’. 7.3 Registers The PCA9665 contains eleven registers which are used to configure the operation of the device as well as to send and receive serial data ...
Page 7
... INDPTR REGISTER write? no yes read/write? no yes I2CDAT REGISTER read/write? no yes I2CCON REGISTER read/write? Rev. 02 — 7 December 2006 PCA9665 2 Fm+ parallel bus to I C-bus controller INDPTR Read/Write 00h R/W 01h R/W 02h R/W 03h R/W 04h R/W 05h W 06h R/W yes I2CCOUNT REGISTER ...
Page 8
... SD7 bit position and the Read/Write bit in the SD0 bit position. The CPU can read from and write to this 8-bit register while the PCA9665 is not in the process of shifting a byte. This occurs when PCA9665 defined state and the serial interrupt fl ...
Page 9
... Section 8.1 “Configuration modes” SD3 SD2 C-bus. A logic 0 corresponds to a LOW level on the bus. 2 C-bus. A Write to the I2CCON register via the PCA9665 2 C-bus controller for 1 0 SD1 SD0 MODE © NXP B.V. 2006. All rights reserved ...
Page 10
... HIGH level. In state C8h, the AA flag can be set again for future address recognition. When the PCA9665 is in the not addressed slave mode, its own slave address is ignored. Consequently, no acknowledge is returned, and a serial interrupt is not requested. Thus, the bus controller can be temporarily released from the I while the bus status is monitored ...
Page 11
... If the STA and STO bits are both set, then a STOP condition is transmitted on the 2 I C-bus, if the PCA9665 master mode. the bus controller then transmits a START condition after the minimum buffer time (t STO = 0 : When the STO bit is reset, no STOP condition will be generated. ...
Page 12
... Description Last Byte control bit. Master/Slave Buffered Receiver mode only PCA9665 does not acknowledge the last received byte PCA9665 acknowledges the last received byte. A future bus transaction must complete the read sequence by not acknowledging the last byte. Number of bytes to be read or written ( bytes). If BC[6:0] is equal ...
Page 13
... NXP Semiconductors 7.3.2.3 The Clock Rate registers, I2CSCLL and I2CSCLH (indirect addresses 02h and 03h) I2CSCLL and I2CSCLH are 8-bit read/write registers. They define the data rate for the PCA9665 when used as a bus master. The actual frequency is determined by t where SCL is HIGH ...
Page 14
... The Parallel Software Reset register, I2CPRESET (indirect address 05h) I2CPRESET is an 8-bit write-only register. Programming the I2CPRESET register allows the user to reset the PCA9665 under software control. The software reset is achieved by writing two consecutive bytes to this register. The first byte must be A5h while the second byte must be 5Ah ...
Page 15
... C-bus frequency (hexadecimal) (kHz) 86 99.9 14 396.8 09 952 C-bus mode. Use of lower values will cause the minimum values to be loaded ---------------------------------------------------------------------------------------------- - SCL T I 2CSCLL osc Rev. 02 — 7 December 2006 PCA9665 2 Fm+ parallel bus SU;STO HIGH LOW AC1 [1] AC[1:0] Mode [2] 00 ...
Page 16
... The Buffered mode allows several instructions to be executed before an Interrupt is generated and before the I2CSTA register is updated. This allows the microcontroller to request a sequence bytes in a single transmission and lets the PCA9665 perform it without having to access the Status Register and the Control Register each time a single command is performed ...
Page 17
... Bit Symbol Value ENSIO must be set to logic 1 to enable the PCA9665. If the AA bit is reset, the PCA9665 will not acknowledge its own slave address in the event of another device becoming master of the bus. (In other words reset, PCA9665 cannot enter a slave mode.) STA, STO, and SI must be reset. Once ENSIO has been set takes about 550 s for the oscillator to start up ...
Page 18
... PCA9665 lost the arbitration and is addressed as a slave receiver (slave mode enabled with • D8h if the PCA9665 lost the arbitration and is addressed as a slave receiver during a General Call sequence (slave mode enabled with and General Call address enabled with I2CADR register) ...
Page 19
... Slave Receiver mode (General Call) any number of data bytes and their associated Acknowledge bits This number (contained in I2CSTA) corresponds 2 ( defined state of the I C-bus. Rev. 02 — 7 December 2006 PCA9665 2 Fm+ parallel bus to I C-bus controller A P 28h F8h (2) ...
Page 20
... X 0 SLA+W will be transmitted; ACK/NACK will be received X 0 SLA+W will be transmitted; ACK/NACK will be received X 0 SLA+R will be transmitted; PCA9665 will be switched to Master Receiver Byte mode X 0 Data byte will be transmitted; ACK/NACK will be received X 0 Repeated START will be transmitted STOP condition will be transmitted; ...
Page 21
... No I2CDAT action Rev. 02 — 7 December 2006 PCA9665 2 Fm+ parallel bus to I Next action taken by the PCA9665 AA MODE X 0 Data byte will be transmitted; ACK/NACK will be received X 0 Repeated START will be transmitted STOP condition will be transmitted; STO flag will be reset ...
Page 22
... PCA9665 lost the arbitration and is addressed as a slave receiver (slave mode enabled with • D8h if the PCA9665 lost the arbitration and is addressed as a slave receiver during a General Call sequence (slave mode enabled with and General Call address enabled with I2CADR register). ...
Page 23
... A continues to corresponding states in Slave Transmitter mode B0h 68h to corresponding states in Slave Receiver mode D8h to corresponding states in Slave Receiver mode (General Call) 2 (1) C-bus. Rev. 02 — 7 December 2006 PCA9665 2 Fm+ parallel bus to I C-bus controller DATA A P 58h F8h (3) S SLA 10h ...
Page 24
... Rev. 02 — 7 December 2006 PCA9665 2 Fm+ parallel bus to I C-bus controller Next action taken by the PCA9665 AA MODE X 0 SLA+R will be transmitted; ACK/NACK bit will be received X 0 SLA+R will be transmitted; ACK/NACK bit will be received X 0 SLA+W will be transmitted; ...
Page 25
... The General Call Address (00h) has been received (General Call address enabled with GC = 1). See status D0h. If the AA bit is reset during a transfer, the PCA9665 will return a not acknowledge (logic 1) on SDA after the next received data byte. While AA is reset, the I does not respond to its own slave address ...
Page 26
... D8h F8h on STOP any number of data bytes and their associated Acknowledge bits This number (contained in I2CSTA) corresponds 2 ( defined state of the I C-bus. Rev. 02 — 7 December 2006 PCA9665 2 Fm+ parallel bus to I C-bus controller A DATA 80h 80h A0h ...
Page 27
... X 0 read data byte Rev. 02 — 7 December 2006 PCA9665 2 Fm+ parallel bus to I C-bus controller Next action taken by the PCA9665 AA MODE 0 0 Data byte will be received and NACK will be returned 1 0 Data byte will be received and ACK will be returned 0 0 Data byte will be received and ...
Page 28
... I2CDAT action Rev. 02 — 7 December 2006 PCA9665 2 Fm+ parallel bus to I C-bus controller Next action taken by the PCA9665 AA MODE 0 0 Data byte will be received and NACK will be returned Data byte will be received and ACK will be returned Switched to not addressed slave mode ...
Page 29
... Defined state when a single byte is transmitted and an ACK is received. (3) Defined state when a single byte is transmitted and a NACK is received. (4) Defined state when a single byte is transmitted and the PCA9665 goes to the non-addressed mode ( and an ACK is received. Fig 10. Format and states in the Slave Transmitter Byte mode (MODE = 0) ...
Page 30
... X 0 action or no I2CDAT action Rev. 02 — 7 December 2006 PCA9665 Fm+ parallel bus to I Next action taken by PCA9665 0 0 Last data byte will be transmitted and ACK/NACK bit will be received 1 0 Data byte will be transmitted; ACK/NACK will be received 0 0 Last data byte will be transmitted and ...
Page 31
... Bit Symbol Value ENSIO must be set to logic 1 to enable the PCA9665. If the AA bit is reset, the PCA9665 will not acknowledge its own slave address in the event of another device becoming master of the bus (in other words reset, the PCA9665 cannot enter a slave mode). ...
Page 32
... PCA9665 lost the arbitration and is addressed as a slave receiver (slave mode enabled with AA = 1). • D8h if the PCA9665 lost the arbitration and is addressed as a slave receiver during a General Call sequence (slave mode enabled with and General Call address enabled with I2CADR register). ...
Page 33
... Slave Receiver mode (General Call) any number of data bytes and their associated Acknowledge bits This number (contained in I2CSTA) corresponds 2 ( defined state of the I C-bus. Rev. 02 — 7 December 2006 PCA9665 2 Fm+ parallel bus to I C-bus controller A P 28h F8h (3) ...
Page 34
... ACK has been received for each of them or until a NACK bit is received. 1 SLA+R will be transmitted. PCA9665 will be switched to Master Receiver Buffered mode BC[6:0] data bytes will be transmitted (until all of them have been sent and an ACK has been received for each of them or until a NACK bit is received) ...
Page 35
... STOP condition followed by a START condition will be transmitted. STO flag will be reset C-bus will be released; PCA9665 will enter the not addressed slave mode C-bus will be released; PCA9665 will enter the slave mode START condition will be transmitted when the bus becomes free. ...
Page 36
... PCA9665 lost the arbitration and is addressed as a slave receiver (slave mode enabled with • D8h if the PCA9665 lost the arbitration and is addressed as a slave receiver during a General Call sequence (slave mode enabled with and General Call address enabled with I2CADR register). ...
Page 37
... A continues B0h to corresponding states in Slave Transmitter mode 68h to corresponding states in Slave Receiver mode D8h to corresponding states in Slave Receiver mode (General Call) 2 (1) C-bus. Rev. 02 — 7 December 2006 PCA9665 Fm+ parallel bus DATA A P DATA 58h F8h (4) S 10h to Master Transmitter mode ...
Page 38
... If ACK bit received, BC[6:0] data bytes will be received, ACK bit will be returned for all of them, except for the last one where NACK bit will be returned. 1 SLA+W will be transmitted; PCA9665 will be switched to Master Transmitter Buffered mode C-bus will be released; PCA9665 will enter slave mode. ...
Page 39
... Next action taken by the PCA9665 1 BC[6:0] data bytes will be received, ACK bit will be returned for all of them 1 BC[6:0] data bytes will be received, ACK bit will be returned for all of them, except for the last one where NACK bit will be returned ...
Page 40
... Symbol Value The upper 7 bits are the master the control bit that allows the PCA9665 to respond or not to the General Call address (00h). When programmed to logic 1, the PCA9665 will acknowledge the General Call address. When programmed to logic 0, the PCA9665 will not acknowledge the General Call address ...
Page 41
... NXP Semiconductors If the LB bit is reset (logic 0), the PCA9665 will return an acknowledge for all the bytes that will be received. The maximum number of bytes that are received in a single sequence is defined by BC[6:0] in I2CCOUNT register as shown in If the LB bit is set (logic 1) during a transfer, the PCA9665 will return a not acknowledge (logic 1) on SDA after receiving the last byte ...
Page 42
... X 1 bytes to be received Next action taken by the PCA9665 Up to BC[6:0] data bytes will be received, ACK bit will be returned for all of them BC[6:0] data bytes will be received, ACK bit will be returned for all of them, except for the last one where NACK bit will be returned (unless master transmitter sends a STOP or Repeated START condition before) ...
Page 43
... X 1 bytes to be received Next action taken by the PCA9665 Up to BC[6:0] data bytes will be received, ACK bit will be returned for all of them BC[6:0] data bytes will be received, ACK bit will be returned for all of them, except for the last one where NACK bit will be returned (unless master transmitter sends a STOP or Repeated START condition before) ...
Page 44
... Next action taken by the PCA9665 Switched to not addressed slave mode; No recognition of own slave address; General Call address will be recognized Switched to not addressed slave mode; Own slave address will be recognized; General Call address will be recognized Switched to not addressed slave mode; ...
Page 45
... Defined state when a NACK is received. The number of bytes transmitted is lower than or equal to the value in the I2CCOUNT register. (4) Defined state after the last byte has been transmitted and the PCA9665 goes to the non-addressed mode ( and an ACK is received. The number of bytes that are transmitted is equal to the value in I2CCOUNT register. ...
Page 46
... PCA9665 switches to the not addressed mode after BC[6:0] bytes have been transmitted BC[6:0] bytes will be transmitted BC[6:0] bytes will be transmitted. PCA9665 switches to the not addressed mode after BC[6:0] bytes have been transmitted BC[6:0] bytes will be transmitted. 1 Switched to not addressed slave mode; No recognition of own slave address; ...
Page 47
... Next action taken by the PCA9665 1 Switched to not addressed slave mode; No recognition of own slave address; General Call address recognized Switched to slave mode; Own slave address will be recognized; General Call address recognized Switched to not addressed slave mode; ...
Page 48
... Load the data bytes in I2CDAT buffer. The different bytes to be sent will be stored in the PCA9665 buffer. There is no protection against writing over a buffer’s boundary. If more than 68 bytes are written to the buffer, the data at address 00h will be overwritten ...
Page 49
... Load the data bytes in I2CDAT buffer. The different bytes to be sent will be stored in the PCA9665 buffer. There is no protection against writing over a buffer’s boundary. If more than 68 bytes are written to the buffer, the data at address 00h will be overwritten. The number of bytes that needs to be loaded in I2CDAT is equal to BC[6:0] in the I2CCOUNT register ...
Page 50
... More sequences (program I2CCOUNT register, load data bytes in I2CDAT buffer, write the I2CCON register to send the data to the I when sequence has been executed) can be performed as long as the master acknowledges the bytes sent by the PCA9665 and Slave Transmitter Buffered mode ends when the I PCA9665 goes to Non-addressed Slave mode. ...
Page 51
... NXP Semiconductors – the SCL line is held LOW by the PCA9665 after the 2 bytes have been sent – the PCA9665 sends an Interrupt, sets and updates I2CSTA register – I2CSTA reads 28h 5. Program I2CCOUNT = 40h (64 bytes to read and Last byte acknowledged). 6. Load I2CDAT with A1h (I 7. Program I2CCON with STA = MODE = 1. – ...
Page 52
... Slave Receiver Buffered mode (regular slave mode and General Call response After Slave Address + W and ACK bit returned for slave address (both in regular mode and when PCA9665 loses arbitration and is addressed as slave) After receiving ‘n’ bytes, ACK bit returned for the ‘n’ bytes After receiving ‘ ...
Page 53
... Buffered modes Data acknowledge/not acknowledge management can be controlled on a byte basis (Byte mode sequence basis (Buffered mode). The PCA9665 can be programmed to respond (ACK) or not (NACK) to two different I is performed based on the different control bits (AA, GC, LB and MODE) and the different modes ...
Page 54
... ACK returned after one byte received Slave Receiver mode • ACK returned after own slave address received • 2 C-bus sequence ACK returned after one byte received Rev. 02 — 7 December 2006 PCA9665 2 Fm+ parallel bus to I C-bus controller © NXP B.V. 2006. All rights reserved ...
Page 55
... BC[6:0] a buffered value) sequence is • in addressed mode, transmitted (after switch to non-addressed bytes sent = BC[6:0] mode after the last byte value buffered sequence is received (after bytes received = BC[6:0] value) PCA9665 2 C-bus controller © NXP B.V. 2006. All rights reserved ...
Page 56
... BC[6:0] value basis = BC[6:0] • in addressed mode, value NACK returned after the • always addressed last byte of a buffered during a buffered sequence received (after sequence bytes received = BC[6:0] value) PCA9665 2 C-bus controller © NXP B.V. 2006. All rights reserved ...
Page 57
... STOP condition 8.8.1 I2CSTA = F8h This status code indicates that the PCA9665 idle state and that no relevant information is available because the serial interrupt flag, SI, is not yet set. This occurs on a STOP condition or during a hardware or software reset event and when the PCA9665 is not involved in a serial transfer ...
Page 58
... I2CSTA = 78h This status code indicates that the SCL line is stuck LOW. 8.9 Some special cases The PCA9665 has facilities to handle the following special cases that may occur during a serial transfer. 8.9.1 Simultaneous repeated START conditions from two masters A repeated START condition may be generated in the Master Transmitter or Master Receiver modes ...
Page 59
... STOP condition. If the SDA line is released by the slave pulling it LOW, a normal START condition is transmitted by the PCA9665, state 08h is entered and the serial transfer continues. If the SDA line is not released by the slave pulling it LOW, then the PCA9665 concludes that there is a bus error, loads 70h in I2CSTA, generates an interrupt signal, and releases the SCL and SDA lines ...
Page 60
... Examples of illegal positions are during the serial transfer of an address byte, a data or an acknowledge bit. The PCA9665 only reacts to a bus error when it is involved in a serial transfer either as a master or an addressed slave. When a bus error is detected, PCA9665 releases the SDA and SCL lines, sets the interrupt fl ...
Page 61
... NXP Semiconductors 8.11 Reset Reset of the PCA9665 to its default state can be performed in 2 different ways: • By holding the RESET pin LOW for a minimum of t • By using the Parallel Software Reset sequence as described in access to INDPTR Indirect Register pointer A[1:0] 00 I2CPRESET register selected D[7:0] WR following byte is ignored ...
Page 62
... Fig 21. Bus timing diagram; Unbuffered Slave Transmitter mode SCL SDA INT (1) 7-bit address R START condition from slave PCA9665 Slave PCA9665 is written to by external master transmitter. (1) As defined in I2CADR register. Fig 22. Bus timing diagram; Unbuffered Slave Receiver mode PCA9665_2 Product data sheet interrupt interrupt first byte ACK ACK ...
Page 63
... SCL SDA INT (1) 7-bit address R START condition from slave receiver Master PCA9665 writes data to slave transmitter. (1) 7-bit address + R byte and number of bytes sent = value programmed in I2CCOUNT register (BC[6:0] Fig 23. Bus timing diagram; Buffered Master Transmitter mode SCL SDA INT 7-bit address R START ...
Page 64
... SDA INT (1) 7-bit address R START condition from slave PCA9665 Slave PCA9665 is written to by external master transmitter. (1) As defined in I2CADR register. (2) Number of bytes received = value programmed in I2CCOUNT register (BC[6:0] Fig 26. Bus timing diagram; Buffered Slave Receiver mode SCL SDA INT 7-bit SWRST Call address ...
Page 65
... C-bus Figure SDA SCL data line stable; data valid Figure 29). S START condition Figure 30). Rev. 02 — 7 December 2006 PCA9665 2 Fm+ parallel bus to I C-bus controller 28). change of data allowed mba607 P STOP condition © NXP B.V. 2006. All rights reserved. SDA SCL mba608 ...
Page 66
... TRANSMITTER/ RECEIVER TRANSMITTER RECEIVER data output by transmitter data output by receiver SCL from master 1 S START condition 2 C-bus Rev. 02 — 7 December 2006 PCA9665 Fm+ parallel bus to I MASTER MASTER TRANSMITTER/ MULTIPLEXER RECEIVER SLAVE not acknowledge acknowledge 2 8 clock pulse for acknowledgement 2 C-bus controller ...
Page 67
... C-bus or SMBus components, where the ‘smart’ device does 2 C-bus port and the designer does not want to ‘bit-bang’ the C-bus port Figure 33, the PCA9665 converts 8-bits of parallel data into a multiple master 2 C-bus port for microcontrollers, microprocessors, custom ASICs, DSPs, etc., 2 C-bus or SMBus components. ...
Page 68
... NXP Semiconductors Fig 33. Adding I 10.3 Add additional I The PCA9665 can be used to convert 8-bit parallel data into additional multiple master capable I microprocessor, custom ASIC, DSP, etc., already have an I more additional I components that cannot be located on the same bus (e.g., 100 kHz and 400 kHz slaves on different buses so that each bus can operate at its maximum potential) ...
Page 69
... V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 4.6 V steady state voltage tolerance on inputs and outputs when no supply voltage is present. PCA9665_2 Product data sheet Fm+ parallel bus to I Conditions any input any input any output operating Rev. 02 — 7 December 2006 PCA9665 2 C-bus controller Min Max Unit 0.3 +4.6 V [1] 0.8 +6 ...
Page 70
... 0 input 5 input/output 3 input/output Rev. 02 — 7 December 2006 PCA9665 2 C-bus controller Min Typ Max 2.3 - 3.6 - 0.1 3 8.0 - 1.8 2 0.8 [1] 2 0.8 [1] 2.0 - 5.5 4.0 7 ...
Page 71
... Fm+ parallel bus to I Table 50 on page 72 for 2.5 V) Min Typ - - - - 10 - [5][6] 250 - Figure PCA9665 2 C-bus controller Max Unit 550 s 550 500 and Figure 40. © NXP B.V. 2006. All rights reserved. ...
Page 72
... RC time constant of the SDA and SCL bus. rst Rev. 02 — 7 December 2006 Fm+ parallel bus to I Table 49 on page 71 for 3.3 V) Min - - 10 [5][6] 250 Figure PCA9665 2 C-bus controller Typ Max Unit - 550 s - 550 550 ...
Page 73
... Dn Fig 36. Reset timing SCL INT Fig 37. Interrupt timing PCA9665_2 Product data sheet as(int) Rev. 02 — 7 December 2006 PCA9665 2 Fm+ parallel bus to I C-bus controller ACK or read cycle rst w(rst) t rst off 30 % 002aab272 ...
Page 74
... Product data sheet t su( su(CE_N) t w(RDL d(DV) float not valid t su( su(CE_N) t w(WRL) WR Rev. 02 — 7 December 2006 PCA9665 Fm+ parallel bus h(CE_N) t w(RDH) t d(QZ) valid float t h(CE_N) t w(WRH) t h(Q) t su(Q) valid 2 C-bus controller 002aac693 002aac692 © NXP B.V. 2006. All rights reserved ...
Page 75
... and V are typical output voltage drops that occur with the output load Rev. 02 — 7 December 2006 PCA9665 2 Fm+ parallel bus to I C-bus controller d(QZL d(QZH outputs outputs ...
Page 76
... SCL signal) in order to IL PCA9665 2 C-bus controller 0.2 V and Unit 2 I C-bus Max 0 1000 kHz - 0. 120 ns - 120 specifi © NXP B.V. 2006. All rights reserved. ...
Page 77
... SU;DAT HD;DAT and Rev. 02 — 7 December 2006 Fm+ parallel bus BUF t t HD;STA SU;STO P S STOP acknowledge bit 0 condition (A) ( VD;DAT VD;ACK PCA9665 2 C-bus controller 002aab271 SU;STO 002aac696 © NXP B.V. 2006. All rights reserved ...
Page 78
... termination resistance should be equal to the output impedance Z T generators. Test data Load Rev. 02 — 7 December 2006 PCA9665 2 Fm+ parallel bus open 500 V O DUT ...
Page 79
... 1.73 0.53 0.36 26.92 6.40 1.30 0.38 0.23 26.54 6.22 0.068 0.021 0.014 1.060 0.25 0.051 0.015 0.009 1.045 0.24 REFERENCES JEDEC JEITA MS-001 SC-603 Rev. 02 — 7 December 2006 PCA9665 2 Fm+ parallel bus 3.60 8.25 10.0 2.54 7.62 3.05 7.80 8.3 0.14 0.32 0.39 ...
Page 80
... detail 1.1 1.1 1.4 0.25 0.25 0.4 1.0 0.043 0.043 0.055 0.01 0.01 0.016 0.039 EUROPEAN PROJECTION PCA9665 2 C-bus controller SOT163 ( 0.9 0 0.035 0.004 0.016 ISSUE DATE 99-12-27 03-02-19 © NXP B.V. 2006. All rights reserved ...
Page 81
... Rev. 02 — 7 December 2006 Fm+ parallel bus detail 6.6 0.75 0.4 1 0.2 0.13 6.2 0.50 0.3 EUROPEAN PROJECTION PCA9665 2 C-bus controller SOT360 ( 0.5 8 0.1 o 0.2 0 ISSUE DATE 99-12-27 03-02-19 © NXP B.V. 2006. All rights reserved ...
Page 82
... 5.1 3.25 5.1 3.25 0.65 2.6 4.9 2.95 4.9 2.95 REFERENCES JEDEC JEITA MO-220 - - - Rev. 02 — 7 December 2006 Fm+ parallel bus detail 0.75 0.05 0.1 2.6 0.1 0.05 0.50 EUROPEAN PROJECTION PCA9665 2 C-bus controller SOT662 ISSUE DATE 01-08-08 02-10-22 © NXP B.V. 2006. All rights reserved ...
Page 83
... In addition, the peak temperature must be low enough that the PCA9665_2 Product data sheet Fm+ parallel bus to I Figure Rev. 02 — 7 December 2006 PCA9665 2 C-bus controller ). If the stg(max) 49) than a PbSn process, thus © NXP B.V. 2006. All rights reserved. ...
Page 84
... MSL: Moisture Sensitivity Level Rev. 02 — 7 December 2006 Fm+ parallel bus 350 220 220 3 ) 350 to 2000 > 2000 260 260 250 245 245 245 peak temperature PCA9665 2 C-bus controller time 001aac844 © NXP B.V. 2006. All rights reserved ...
Page 85
... DBS, DIP, HDIP, RDBS, SDIP, SIL [4] Through-hole-surface PMFP mount PCA9665_2 Product data sheet [1] Soldering method Wave suitable suitable not suitable Rev. 02 — 7 December 2006 PCA9665 Fm+ parallel bus to I [2] Reflow [3] not suitable 2 C-bus controller Dipping suitable © NXP B.V. 2006. All rights reserved ...
Page 86
... Wave [5] , LBGA, not suitable [5] , TFBGA, not suitable , SO, SOJ suitable not recommended not recommended [10] [10] , WQCCN..L not suitable Rev. 02 — 7 December 2006 PCA9665 2 Fm+ parallel bus to I C-bus controller …continued [2] Reflow suitable [6] suitable suitable [7][8] suitable [9] suitable not suitable © NXP B.V. 2006. All rights reserved. ...
Page 87
... Table note 2: equation denominator close parenthesis (Typ) changed from 1 2 (Typ) changed from 2 2 ”: , power-on initialization time” init(po) Table note 4 PCA9665 2 C-bus controller Supersedes PCA9665_1 th © NXP B.V. 2006. All rights reserved ...
Page 88
... Change notice ”: from (Typ) “<tbd>” to (Max) “550 ns” from (Typ) “<tbd>” to (Max) “20 ns” modified (at switch, “6.0 V” changed to “V 2” DD and Table - PCA9665 2 C-bus controller Supersedes 2” DD 53. - © NXP B.V. 2006. All rights reserved ...
Page 89
... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 02 — 7 December 2006 PCA9665 2 Fm+ parallel bus to I C-bus controller © NXP B.V. 2006. All rights reserved ...
Page 90
... The Time-out register, I2CTO (indirect address 04h 7.3.2.5 The Parallel Software Reset register, I2CPRESET (indirect address 05h 7.3.2.6 The I C-bus mode register, I2CMODE (indirect address 06h PCA9665 modes 8.1 Configuration modes 8.1.1 Byte mode 8.1.2 Buffered mode . . . . . . . . . . . . . . . . . . . . . . . . 16 8.2 Operating modes . . . . . . . . . . . . . . . . . . . . . . 16 8.3 Byte mode 8.3.1 Master Transmitter Byte mode . . . . . . . . . . . . 17 8 ...
Page 91
... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2006. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCA9665 2 C-bus controller All rights reserved. Date of release: 7 December 2006 Document identifier: PCA9665_2 ...