pck9446 NXP Semiconductors, pck9446 Datasheet

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pck9446

Manufacturer Part Number
pck9446
Description
2.5 V And 3.3 V Lvcmos Clock Fan-out Buffer
Manufacturer
NXP Semiconductors
Datasheet

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1. General description
2. Features
The PCK9446 is a 2.5 V and 3.3 V compatible 1 : 10 clock distribution buffer designed for
low-voltage mid-range to high-performance telecom, networking and computing
applications. Both 3.3 V, 2.5 V and dual supply voltages are supported for mixed-voltage
applications. The PCK9446 offers 10 low skew outputs and 2 selectable inputs for clock
redundancy. The outputs are configurable and support 1 : 1 and 1 : 2 output to input
frequency ratios. The PCK9446 is specified for the extended temperature range of
The PCK9446 is a full static design supporting clock frequencies up to 250 MHz. The
signals are generated and retimed on-chip to ensure minimal skew between the three
output banks. Two independent LVCMOS compatible clock inputs are available. This
feature supports redundant clock sources or the addition of a test clock into the system
design. Each of the three output banks can be individually supplied by 2.5 V or 3.3 V
supporting mixed voltage applications. The FSELx pins choose between division of the
input reference frequency by one or two. The frequency divider can be set individually for
each of the three output banks. The PCK9446 can be reset and the outputs are disabled
by deasserting the MR/OE pin (logic HIGH state). Asserting OE will enable the outputs.
All inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels
with the capability to drive terminated 50
PCK9456 specification for a 1 : 10 mixed voltage buffer with LVPECL compatible inputs.
For series terminated transmission lines, each of the PCK9446 outputs can drive one or
two traces giving the devices an effective fan-out of 1 : 20. The device is packaged in a
32-lead LQFP package which has a 7 mm
pin spacing.
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40 C to +85 C.
PCK9446
2.5 V and 3.3 V LVCMOS clock fan-out buffer
Rev. 01 — 10 April 2006
Configurable 10 outputs LVCMOS clock distribution buffer
Compatible to single, dual and mixed 3.3 V/2.5 V voltage supply
Wide range output clock frequency up to 250 MHz
Designed for mid-range to high-performance telecom, networking and computer
applications
Supports applications requiring clock redundancy
Maximum output skew of 200 ps (100 ps within one bank)
Selectable output configurations per output bank
3-stateable outputs
32-lead LQFP packaging
Ambient operating temperature range of 40 C to +85 C
transmission lines. Please refer to the
7 mm body size with a conservative 0.8 mm
Product data sheet

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pck9446 Summary of contents

Page 1

... V and 3.3 V LVCMOS clock fan-out buffer Rev. 01 — 10 April 2006 1. General description The PCK9446 is a 2.5 V and 3.3 V compatible clock distribution buffer designed for low-voltage mid-range to high-performance telecom, networking and computing applications. Both 3.3 V, 2.5 V and dual supply voltages are supported for mixed-voltage applications. The PCK9446 offers 10 low skew outputs and 2 selectable inputs for clock redundancy. The outputs are confi ...

Page 2

... Philips Semiconductors 3. Ordering information Table 1. Type number PCK9446BD 4. Functional diagram Fig 1. Logic diagram of PCK9446 PCK9446_1 Product data sheet Ordering information Package Name Description LQFP32 plastic low profile quad flat package; 32 leads; body CLK0 CLK1 1 CLK_SEL ...

Page 3

... O LVCMOS 23, 21 LVCMOS 10, 12, 14 LVCMOS . CC Rev. 01 — 10 April 2006 PCK9446 2.5 V and 3.3 V LVCMOS clock fan-out buffer 24 GND 23 QB0 22 VCCB 21 QB1 20 GND 19 QB2 18 VCCB 17 VCCC 002aaa706 Description clock input select LVCMOS clock inputs ...

Page 4

... A outputs (VCCA pins the positive power supply of the bank B outputs (VCCB pins internally connected to V CCB is the positive power supply of the bank C outputs (VCCC pins). V Rev. 01 — 10 April 2006 PCK9446 2.5 V and 3.3 V LVCMOS clock fan-out buffer 1 CLK1 frequency on bank A outputs = f ref ...

Page 5

... Operating conditions Parameter supply voltage supply voltage (bank A) supply voltage (bank B) supply voltage (bank C) ambient temperature Rev. 01 — 10 April 2006 PCK9446 2.5 V and 3.3 V LVCMOS clock fan-out buffer Conditions Min Max 0.3 +4 ...

Page 6

... PD I maximum quiescent current q(max) Z output impedance o V termination voltage T [1] The PCK9446 is capable of driving 50 transmission line to a termination voltage of V [2] Input pull-up/pull-down resistors influence input current. Table 8. Static characteristics (2 + amb CC Symbol Parameter ...

Page 7

... © Koninklijke Philips Electronics N.V. 2006. All rights reserved. PCK9446 Max Unit 250 MHz 250 MHz 125 MHz 75 % 4 150 ps 200 ps 1.2 ns 2.2 ns 500 ps 55 ...

Page 8

... 2 3.3 V CC(bankC) Min Typ - - - - - - - - - - © Koninklijke Philips Electronics N.V. 2006. All rights reserved. PCK9446 Max Unit - MHz - MHz - MHz 75 % 5 150 ps 200 ps 1.2 ns 3.0 ns 500 3.0 ns 1.0 ns 3.0 ns 1.0 ns [1][ ...

Page 9

... DC current and thus only a single terminated line can be driven by each output of the PCK9446 clock driver. For the series terminated case however there current draw, thus the outputs can drive multiple series terminated lines. ...

Page 10

... Philips Semiconductors The waveform plots of versus two lines. In both cases the drive capability of the PCK9446 output buffer is more than sufficient to drive 50 measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the PCK9446. The output waveform in shows a step in the waveform ...

Page 11

... Philips Semiconductors Fig 5. Optimized dual line termination 12. Test information GENERATOR Fig 6. CLK0, CLK1 PCK9446 AC test reference for (1) 2.4 V when V = 3.3 V; 1.8 V when V CC (2) 0.55 V when V = 3.3 V; 0.6 V when V CC Fig 7. Output transition time test reference CLK0, CLK1 Fig 9. Propagation delay (t ...

Page 12

... Rev. 01 — 10 April 2006 2.5 V and 3.3 V LVCMOS clock fan-out buffer detail 9.15 0.75 0.9 1 0.2 0.25 0.1 8.85 0.45 0.5 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2006. All rights reserved. PCK9446 SOT358 ( 0.5 0 ISSUE DATE 03-02-25 05-11- ...

Page 13

... PCK9446_1 Product data sheet 2.5 V and 3.3 V LVCMOS clock fan-out buffer 2 called small/thin packages. Rev. 01 — 10 April 2006 PCK9446 3 350 mm so called © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...

Page 14

... LBGA, LFBGA, SQFP, [3] , TFBGA, VFBGA, XSON , SO, SOJ [8] [9] [8] , PMFP , WQCCN.. measured in the atmosphere of the reflow oven. The package Rev. 01 — 10 April 2006 PCK9446 2.5 V and 3.3 V LVCMOS clock fan-out buffer Soldering method Wave not suitable [4] not suitable suitable [5][6] not recommended [7] not recommended not suitable © ...

Page 15

... Abbreviations Description Low Voltage Complementary Metal Oxide Silicon Low Voltage Positive Emitter Coupled Logic Data sheet status Product data sheet Rev. 01 — 10 April 2006 PCK9446 2.5 V and 3.3 V LVCMOS clock fan-out buffer Change notice Supersedes - - © Koninklijke Philips Electronics N.V. 2006. All rights reserved. ...

Page 16

... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Rev. 01 — 10 April 2006 PCK9446 2.5 V and 3.3 V LVCMOS clock fan-out buffer © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...

Page 17

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © Koninklijke Philips Electronics N.V. 2006. For more information, please visit: http://www.semiconductors.philips.com. For sales office addresses, email to: sales.addresses@www.semiconductors.philips.com. PCK9446 All rights reserved. Date of release: 10 April 2006 Document identifier: PCK9446_1 ...

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