SCANPSC110F National Semiconductor, SCANPSC110F Datasheet

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SCANPSC110F

Manufacturer Part Number
SCANPSC110F
Description
SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port
Manufacturer
National Semiconductor
Datasheet

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© 1999 National Semiconductor Corporation
SCANPSC110F
SCAN Bridge Hierarchical and Multidrop Addressable
JTAG Port (IEEE1149.1 System Test Support)
General Description
The SCANPSC110F Bridge extends the IEEE Std. 1149.1
test bus into a multidrop test bus environment. The advan-
tage of a hierarchical approach over a single serial scan
chain is improved test throughput and the ability to remove a
board from the system and retain test access to the remain-
ing modules. Each SCANPSC110F Bridge supports up to 3
local scan rings which can be accessed individually or com-
bined serially. Addressing is accomplished by loading the in-
struction register with a value matching that of the Slot in-
puts. Backplane and inter-board testing can easily be
accomplished by parking the local TAP Controllers in one of
the stable TAP Controller states via a Park instruction. The
32-bit TCK counter enables built in self test operations to be
performed on one port while other scan chains are simulta-
neously tested.
Features
n True IEEE1149.1 hierarchical and multidrop addressable
Connection Diagrams
TRI-STATE
capability
®
is a registered trademark of National Semiconductor Corporation.
CDIP and Flatpak
28-Pin
DS100327-1
DS100327
n The 6 slot inputs support up to 59 unique addresses, a
n 3 IEEE 1149.1-compatible configurable local scan ports
n Mode Register allows local TAPs to be bypassed,
n 32-bit TCK counter
n 16-bit LFSR Signature Compactor
n Local TAPs can be tri-stated via the OE input to allow
n The IP version of this device supports features not
Broadcast Address, and 4 Multi-cast Group Addresses
selected for insertion into the scan chain individually, or
serially in groups of two or three
an alternate test master to take control of the local TAPs
described in this datasheet such as 8 slot inputs for
enhanced address capability and additional instructions.
For a completed description of the additional instructions
supported, refer to the SCANPSC110 supplemental
datasheet.
Pin Assignment for LCC
DS100327-2
October 1999
www.national.com

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SCANPSC110F Summary of contents

Page 1

... Each SCANPSC110F Bridge supports local scan rings which can be accessed individually or com- bined serially. Addressing is accomplished by loading the in- struction register with a value matching that of the Slot in- puts ...

Page 2

... L1 Local Local is used to describe IEEE Std. 1149.1 compliant scan rings and the SCANPSC110F Bridge Test Access Port that drives them. The term “local” was adopted from the system test architecture that the ’PSC110F Bridge will most commonly be used in; namely, a system test backplane with a ’ ...

Page 3

... TABLE 2. Detailed Pin Description Table Description BACKPLANE TEST MODE SELECT: Controls sequencing through the TAP Controller of the SCANPSC110F Bridge. Also controls sequencing of the TAPs which are on the three (3) local scan chains. BACKPLANE TEST DATA INPUT: All backplane scan data is supplied to the ’ ...

Page 4

... GND Ground potential 14, 21 Note 1: All pins are active HIGH unless otherwise noted. Overview of SCANPSC110F Bridge Functions FIGURE 1. SCANPSC110F Bridge Architecture SCANPSC110F BRIDGE ARCHITECTURE Figure 1 shows the basic architecture of the ’PSC110F. The device’s major functional blocks are illustrated here. The TAP Controller, a 16-state state machine, is the central con- trol for the device ...

Page 5

... Functions (Continued) In multi-drop scan systems, a scan tester can select indi- vidual ’PSC110Fs for participation in upcoming scan opera- tions. ’PSC110F “selection” is accomplished by simulta- neously scanning a device address out to multiple FIGURE 2. SCANPSC110F Bridge State Machines The ’PSC110F contains three distinct state-machines (see Figure 2 ). The first of these is the TAP-control state-machine, which is used to drive the ’ ...

Page 6

... ADDR = 6-bit address in the Instruction Register SLOT = Static address in the ’PSC110F Selection Controller FIGURE 3. State Machine for SCANPSC110F Bridge Selection Controller FIGURE 4. Local SCANPSC110F Bridge Port Configuration State Machine The ’PSC110F’s scan port-configuration state-machine is used to control the insertion of local scan ports into the over- all scan chain, or the isolation of local ports from the chain. From the perspective of a system’ ...

Page 7

... Level-2 instructions for functions other than local scan port confguration. These instructions provide access to and control of various regis- ters within the ’PSC110F. This set instructions includes: FIGURE 5. Relationship Between SCANPSC110F Bridge State Machines BYPASS CNTRSEL EXTEST ...

Page 8

... Register Set The SCANPSC110F Bridge includes a number of registers which are used for ’PSC110F selection and configuration, scan data manipulation, and scan-support operations. These registers can be grouped as shown in Table 3 . ...

Page 9

... Hierarchical Test Support Multiple SCANPSC110F Bridges can be used to assemble a hierarchical boundary-scan tree. In such a configuration, the system tester can configure the local ports of a set of ’PSC110Fs connect a specific set of local scan-chains to the active scan chain. Using this capability, the tester can selectively communicate with specific portions of a target system. The tester’ ...

Page 10

... Level 1 Protocol (Continued) TABLE 4. SCANPSC110F Bridge Address Modes Address Types Hex Address (Note 2) Direct Address Broadcast Address Multi-Cast Group 0 Multi-Cast Group 1 Multi-Cast Group 2 Multi-Cast Group 3 Note 2: Hex address ’7X’, ’BX’, or ’FX’ may be used instead of ’3X’. Note 3: Only the six (6) LSB’s of the address is compared to the S DIRECT ADDRESSING The ’ ...

Page 11

... FIGURE 7. Broadcast Addressing: Address Loaded into Instruction Register FIGURE 8. Multi-Cast Addressing: Address Loaded into Instruction Register Level 2 Protocol Once the SCANPSC110F Bridge has been successfully ad- dressed and selected, its internal registers may be accessed via Level-2 Protocol. Level-2 Protocol is compliant to IEEE Std. 1149.1 TAP protocol with one exception: if the ’ ...

Page 12

Level 2 Protocol (Continued) 1. Instructions that insert a ’PSC110F register into the ac- tive scan chain so that the register can be captured or updated (BYPASS, SAMPLE/PRELOAD, EXTEST, ID- CODE, MODESEL, MCGRSEL, LFSRSEL, CNTRSEL). 2. Instructions that configure local ...

Page 13

Level 2 Protocol (Continued) one of the TAP Controller pause states. A local port does not become parked until the ’PSC110F’s TAP Controller is se- quenced through Exit1-DR/IR into the Update-DR/IR state. When the ’PSC110F TAP Controller is in the ...

Page 14

... The instruction shift register is an 8-bit register that is in se- ries with the scan chain whenever the TAP Controller of the SCANPSC110F Bridge is in the Shift-IR state. Upon exiting the Capture-IR state, the value “XXXXXX01” is captured into the instruction register, where “XXXXXX” represents the value on the S inputs ...

Page 15

Register Descriptions (Continued) TABLE 7. Mode Register Control of LSPN Mode Register XXX0X000 XXX0X001 XXX0X010 XXX0X011 XXX0X100 XXX0X101 XXX0X110 XXX0X111 XXX1XXXX X = don’t care Register = ’PSC110F instruction register or any of the ’PSC110F test data registers PAD = ...

Page 16

... Special Features BIST SUPPORT The sequence of instructions to run BIST testing on a parked SCANPSC110F Bridge port is as follows: 1. Pre-load the Boundary register of the device under test if needed. 2. Initialize the TCK counter to 00000000 Hex. Note that the TCK counter is initialized to 00000000 Hex upon Test-Logic-Reset , so this step may not be necessary. 3. Issue the CNTRON instruction to the ’ ...

Page 17

Special Features (Continued) Update-IR were Select-DR , TMS would remain low and L synchronization would not occur until the ’PSC110F TAP Controller entered the Run-Test/Idle state, as shown in Fig- ure 11 . Each local port has its own Local ...

Page 18

... V Maximum Low OL (TDO ) Output Voltage B www.national.com (Note 5) ESD Last Passing Voltage (Min) Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (V SCANPSC110F −20 mA Input Voltage (V I +20 mA Output Voltage (V −0. +0.5V CC Operating Temperature (T Military −20 mA Minimum Input Edge Rate dV/dt +20 mA SCAN “F” Series Devices − ...

Page 19

DC Electrical Characteristics Symbol Parameter I (OE, Maximum Input IN TCK , S ) Leakage Current B (0–5) I Maximum Input IN, MAX (TRST, TDI , Leakage Current Ln TDI , TMS ) Maximum Input IN, MAX ...

Page 20

AC Electrical Characteristics Symbol Parameter t , Propagation Delay PHL t TCK to TCK PLH B Ln TCK to TCK Propagation Delay PHL t TCK to TDO PLH B Ln TCK to TDO ...

Page 21

AC Electrical Characteristics Symbol Parameter t Setup Time S TMS to TCK Hold Time H TMS to TCK Setup Time S TDI to TCK Hold Time H TdI to TCK B ...

Page 22

... C Output Pin Capacitance OUT C Power Dissipation Capacitance PD AC Waveforms FIGURE 13. Waveforms for an Unparked SCANPSC110F Bridge in the SHIFT-DR (IR) TAP Controller State Note A: V and V are measured with respect to ground reference. OHV OLP Note B: Input pulses have the following characteristics MHz, t FIGURE 14. Quiet Output Noise Voltage Waveform www ...

Page 23

AC Waveforms (Continued) FIGURE 16. Output Enable Waveforms FIGURE 15. Reset Waveforms 23 DS100327-18 DS100327-19 www.national.com ...

Page 24

... FIGURE 17. IEEE 1149.1 TAP Controller State Diagram Applications Example FIGURE 18. Boundary Scan Backplane with 10 Card Slots, 8 Slots Are Filled with Boards The following sequence gives an example of how one might use the SCANPSC110F Bridge to perform 1149.1 operations www.national.com DS100327-17 via a multi-drop scan backplane. The system involved has 10 card slots which are filled with modules, and 2 slots are empty ...

Page 25

... Applications Example (Continued) More Information can be found in Application Notes: AN-1023 Structural System Test via IEEE Std. 1149.1 with SCANPSC110F Hierarchical and Multidrop Ad- dressable JTAG Port AN-1022 Boundary Scan, An Enabling Technology for System Level Embedded Test 1. After the system is powered up a level-1 reset is per- formed via the TRST input. All TAP Controllers (both ’ ...

Page 26

Applications Example (Continued) 8. Assume that boards # and # 8 are identical, so that it is possible to test them simultaneously. The tester first addresses Board # 6. Next the MCGRSEL instruction is issued to place ...

Page 27

Applications Example (Continued) 27 www.national.com ...

Page 28

Physical Dimensions inches (millimeters) unless otherwise noted www.national.com 28-Pin Leadless Chip Carrier (LCC) NS Package Number E28A 28-Pin Ceramic DIP NS Package Number J28A 28 ...

Page 29

... NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant ...

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