WM8501 Wolfson Microelectronics plc, WM8501 Datasheet
WM8501
Available stocks
Related parts for WM8501
WM8501 Summary of contents
Page 1
... It is designed for audio applications that require a high voltage output along with enhanced load drive capability. The WM8501 supports data input word lengths from 16 to 24-bits and sampling rates up to 192kHz. The WM8501 consists of a serial interface port, digital interpolation filters, multi-bit sigma delta modulators and stereo DAC in a 14- lead SOIC package ...
Page 2
... WM8501 DESCRIPTION ............................................................................................................1 FEATURES..................................................................................................................1 APPLICATIONS ..........................................................................................................1 BLOCK DIAGRAM ......................................................................................................1 TABLE OF CONTENTS ..............................................................................................2 PIN CONFIGURATION................................................................................................3 ORDERING INFORMATION .......................................................................................3 PIN DESCRIPTION .....................................................................................................4 ABSOLUTE MAXIMUM RATINGS..............................................................................5 RECOMMENDED OPERATING CONDITIONS ..........................................................5 ELECTRICAL CHARACTERISTICS ...........................................................................6 MASTER CLOCK TIMING .................................................................................................. 7 DIGITAL AUDIO INTERFACE ............................................................................................ 7 DEVICE DESCRIPTION..............................................................................................9 GENERAL INTRODUCTION .............................................................................................. 9 DAC CIRCUIT DESCRIPTION ........................................................................................... 9 CLOCKING SCHEMES .....................................................................................................10 DIGITAL AUDIO INTERFACE ...........................................................................................10 AUDIO DATA SAMPLING RATES.....................................................................................12 HARDWARE CONTROL MODES ...
Page 3
... PIN CONFIGURATION ORDERING INFORMATION TEMPERATURE DEVICE RANGE o WM8501GED/V -40 to +85 o WM8501GED/RV -40 to +85 Note: Reel quantity = 3,000 w PACKAGE 14-lead SOIC C (Pb-free) 14-lead SOIC C (Pb-free, tape and reel) MOISTURE SENSITIVITY PEAK SOLDERING LEVEL TEMPERATURE 260°C MSL3 260°C MSL3 PD, Rev 4.2, July 2009 WM8501 3 ...
Page 4
... WM8501 PIN DESCRIPTION PIN NAME 1 LRCLK Digital input DIN Digital input 2 3 BCLK Digital input 4 ENABLE Digital input 5 VMID Analogue output 6 ROUT Analogue output 7 AGND Supply 8 AVDD Supply LOUT Analogue output 9 DGND Digital Supply 10 11 DVDD Digital Supply 12 DEEMPH Digital input ...
Page 5
... Digital supply range Analogue supply range Ground AGND, DGND Difference DGND to AGND Note: Digital supply DVDD must never be more than 0.3V greater than AVDD for normal operation of the device. w SYMBOL TEST CONDITIONS DVDD AVDD WM8501 MIN MAX -0.3V +7V -0.3V +7V DGND -0.3V DVDD +0.3V 38.462MHz -40 C +85 C ...
Page 6
... WM8501 ELECTRICAL CHARACTERISTICS Test Conditions AVDD = 5V, DVDD = 3.3V, GND = 0V, T PARAMETER Digital Logic Levels (TTL Levels) Input LOW level Input HIGH level Output LOW Output HIGH Analogue Reference Levels Reference voltage (VMID) Potential divider resistance DAC Output (Load = 10k . 50pF) 0dBFs Full scale output voltage ...
Page 7
... MCLK Master clock cycle time MCLK Duty cycle Time from MCLK stopping to power down. DIGITAL AUDIO INTERFACE Figure 2 Digital Audio Data Timing w t MCLKL t MCLKH t MCLKY SYMBOL TEST CONDITIONS t MCLKH t MCLKL t MCLKY WM8501 MIN TYP MAX UNIT 40:60 60:40 1.5 12 PD, Rev 4.2, July 2009 s 7 ...
Page 8
... WM8501 Test Conditions o VDD = 5V, GND = 0V + 48kHz, MCLK = 256fs unless otherwise stated. A PARAMETER SYMBOL Audio Data Input Timing Information BCLK cycle time t BCY BCLK pulse width high t BCH BCLK pulse width low t BCL LRCLK set-up time to BCLK t LRSU rising edge ...
Page 9
... The device is packaged in a small 14-pin SOIC. DAC CIRCUIT DESCRIPTION The WM8501 DAC is designed to allow playback of 24-bit PCM audio or similar data with high resolution and low noise and distortion. Sample rates up to 192kHz may be used, with much lower sample rates being acceptable provided that the ratio of sample rate (LRCLK) to master clock (MCLK) is maintained at one of the required rates ...
Page 10
... Master Clock. The external master clock can be applied directly through the MCLK input pin with no configuration necessary for sample rate selection. Note that on the WM8501, MCLK is used to derive clocks for the DAC path. The DAC path consists of DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the DAC ...
Page 11
... Figure 4 Right Justified Mode Timing Diagram DSP MODE A DSP compatible, time division multiplexed format is also supported by the WM8501. This format is of the type where a ‘synch’ pulse is followed by two data words (left and right) of predetermined word length. (16-bits). The ‘synch’ pulse replaces the normal duration LRCLK, and DSP mode is auto-detected by the shorter than normal duration of the LRCLK ...
Page 12
... Figure 6 DSP Mode B Timing AUDIO DATA SAMPLING RATES The master clock for WM8501 supports audio sampling rates from 128fs to 768fs, where fs is the audio sampling frequency (LRCLK) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The master clock is used to operate the digital filters and the noise shaping circuits. ...
Page 13
... Note 2. For data widths greater than 24 bits, the LSB’s will be truncated and the most significant 24 bits will be used by the internal processing exactly 16 BCLK cycles occur in both the low and high period of LRCLK the WM8501 will assume the data is 16-bit and accept the data accordingly. INPUT DSP FORMAT SELECTION ...
Page 14
... WM8501 DIGITAL FILTER CHARACTERISTICS PARAMETER Passband Edge Passband Ripple Stopband Attenuation Table 5 Digital Filter Characteristics DAC FILTER RESPONSES 0 -20 -40 -60 -80 -100 -120 0 0.5 1 1.5 Frequency (Fs) Figure 7 DAC Digital Filter Frequency Response - 44.1, 48 and 96kHz 0 -20 -40 -60 -80 0 0.2 0.4 Frequency (Fs) Figure 9 DAC Digital Filter Frequency Response - 192kHz ...
Page 15
... Figure 15 De-Emphasis Frequency Response (48kHz 0.5 0 -0.5 -1 -1 Figure 12 De-Emphasis Error (32kHz) 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0 Figure 14 De-Emphasis Error (44.1kHz) 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0 Figure 16 De-Emphasis Error (48kHz) WM8501 Frequency (kHz Frequency (kHz Frequency (kHz) PD, Rev 4.2, July 2009 ...
Page 16
... WM8501 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 17 External Component Diagram In an application where ENABLE is fed directly from VDD rather than a dedicated control line, resistor R3 and capacitor C9 are used on the ENABLE pin to introduce a short delay in the Low to High transition of ENABLE. This will ensure the pin goes high after power supplies have had time to settle (see “ ...
Page 17
... Production Data POWER UP/DOWN SEQUENCE POWER UP/DOWN SEQUENCE For click free operation, the WM8501 should be powered up and down in a specific sequence. Power-up: 1. Power up AVDD and DVDD and wait to settle 2. Turn on clocks and data (MCLK, BCLK, LRCLK, SDATA) 3. Switch ENABLE pin from low to high Power-down: 1 ...
Page 18
... WM8501 PCB LAYOUT RECOMMENDATIONS Care should be taken in the layout of the PCB that the WM8501 mounted to. The following notes will help in this respect: 1. The VDD supply to the device should be as noise free as possible. This can be accomplished to a large degree with a 10uF bulk capacitor placed locally to the device and a ...
Page 19
... D. MEETS JEDEC.95 MS-012, VARIATION = AB. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS SEATING PLANE -C- Dimensions (Inches) MIN MAX 1.75 0.0532 0.0688 0.25 0.0040 0.0098 0.51 0.0130 0.0200 0.25 0.0075 0.0098 8.75 0.3367 0.3444 4.00 0.1497 0.1574 0.05 BSC 6.20 0.2284 0.2440 0.50 0.0099 0.0196 1.27 0.0160 0.0500 DM001 PD, Rev 4.2, July 2009 WM8501 19 ...
Page 20
... WM8501 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice ...