ATMEGA48PV-10MU Atmel, ATMEGA48PV-10MU Datasheet - Page 321

• Manufacturer Part Number: ATMEGA48PV-10MU
• Description: MCU AVR 4K ISP FLASH 10MHZ 32QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA48PV-10MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Processor Series: ATMEGA48x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8025L–AVR–7/10
Figure 28-7. Parallel Programming Timing, Including some General Timing Requirements
Figure 28-8. Parallel Programming Timing, Loading Sequence with Timing Requirements
Note:
Figure 28-9. Parallel Programming Timing, Reading Sequence (within the Same Page) with
Note:
XTAL1
DATA
(DATA, XA0/1, BS1, BS2)
BS1
XA0
XA1
OE
PAGEL
XTAL1
1. The timing requirements shown in
1. The timing requirements shown in
DATA
BS1
XA0
XA1
ing operation.
ing operation.
Data & Contol
Timing Requirements
RDY/BSY
ADDR0 (Low Byte)
LOAD ADDRESS
PAGEL
(LOW BYTE)
XTAL1
ADDR0 (Low Byte)
LOAD ADDRESS
(LOW BYTE)
WR
t
XLOL
t
OLDV
t
t
BVPH
DVXH
(1)
(LOW BYTE)
LOAD DATA
DATA (Low Byte)
t
t
XHXL
PHPL
DATA (Low Byte)
READ DATA
(LOW BYTE)
Figure 28-7
Figure 28-7
t
t
t
t
t
XLXH
XLDX
XLWL
PLBX
PLWL
t
BVDV
(i.e., t
(i.e., t
t
ATmega48P/88P/168P
(HIGH BYTE)
BVWL
LOAD DATA
DATA (High Byte)
DVXH
DVXH
(HIGH BYTE)
READ DATA
t
t
DATA (High Byte)
XLPH
WLWH
WLRL
LOAD DATA
, t
, t
XHXL
XHXL
, and t
, and t
t
PLXH
t
OHDZ
t
WLBX
XLDX
XLDX
LOAD ADDRESS
LOAD ADDRESS
(LOW BYTE)
(LOW BYTE)
ADDR1 (Low Byte)
) also apply to read-
) also apply to load-
ADDR1 (Low Byte)
t
WLRH
(1)
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