PIC24FJ16GA002-E/ML Microchip Technology, PIC24FJ16GA002-E/ML Datasheet

IC PIC MCU FLASH 16K 28-QFN

PIC24FJ16GA002-E/ML

Manufacturer Part Number
PIC24FJ16GA002-E/ML
Description
IC PIC MCU FLASH 16K 28-QFN
Manufacturer
Microchip Technology
Series
PIC® 24Fr

Specifications of PIC24FJ16GA002-E/ML

Program Memory Type
FLASH
Program Memory Size
16KB (5.5K x 24)
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
21
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
21
Number Of Timers
5
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, MA240013, AC164127, DM300027, DV164033, DM240002
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Part Number:
PIC24FJ16GA002-E/ML
Manufacturer:
Microchip Technology
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PIC24FJ16GA002-E/ML
Manufacturer:
Microchip Technology
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1.0
This document defines the programming specification
for the PIC24FJXXXGA0XX family of 16-bit micro-
controller devices. This programming specification is
required only for those developing programming support
for the PIC24FJXXXGA0XX family. Customers using
only one of these devices should use development
tools that already
programming.
This specification includes programming specifications
for the following devices:
2.0
There
PIC24FJXXXGA0XX family of devices discussed in
this programming specification. They are:
• In-Circuit Serial Programming™ (ICSP™)
• Enhanced In-Circuit Serial Programming
The ICSP programming method is the most direct
method to program the device; however, it is also the
slower of the two methods. It provides native, low-level
programming capability to erase, program and verify
the chip.
© 2008 Microchip Technology Inc.
• PIC24FJ16GA002
• PIC24FJ16GA004
• PIC24FJ32GA002
• PIC24FJ32GA004
• PIC24FJ48GA002
• PIC24FJ48GA004
• PIC24FJ64GA002
• PIC24FJ64GA004
• PIC24FJ64GA006
• PIC24FJ64GA008
• PIC24FJ64GA010
(Enhanced ICSP)
PIC24FJXXXGA0XX Flash Programming Specification
are
DEVICE OVERVIEW
PROGRAMMING OVERVIEW
OF THE PIC24FJXXXGA0XX
FAMILY
two
methods
provide
• PIC24FJ96GA006
• PIC24FJ96GA008
• PIC24FJ96GA010
• PIC24FJ128GA006
• PIC24FJ128GA008
• PIC24FJ128GA010
of
support for device
programming
PIC24FJXXXGA0XX
the
The
(Enhanced ICSP) protocol uses a faster method that
takes advantage of the programming executive, as
illustrated in Figure 2-1. The programming executive
provides all the necessary functionality to erase, pro-
gram and verify the chip through a small command set.
The command set allows the programmer to program
the PIC24FJXXXGA0XX devices without having to
deal with the low-level programming protocols of the
chip.
FIGURE 2-1:
This specification is divided into major sections that
describe the programming methods independently.
Section 4.0 “Device Programming – Enhanced
ICSP” describes the Run-Time Self-Programming
(RTSP) method. Section 3.0 “Device Programming –
ICSP” describes the In-Circuit Serial Programming
method.
2.1
All devices in the PIC24FJXXXGA0XX family are dual
voltage supply designs: one supply for the core and
peripherals and another for the I/O pins. A regulator is
provided on-chip to alleviate the need for two external
voltage supplies.
All of the PIC24FJXXXGA0XX devices power their core
digital logic at a nominal 2.5V. To simplify system
design, all devices in the PIC24FJXXXGA0XX family
incorporate an on-chip regulator that allows the device
to run its core logic from V
Programmer
Enhanced
Power Requirements
In-Circuit
PROGRAMMING SYSTEM
OVERVIEW FOR
ENHANCED ICSP™
DD
.
PIC24FJXXXGA0XX
Serial
On-Chip Memory
Programming
Executive
DS39768D-page 1
Programming

PIC24FJ16GA002-E/ML Summary of contents

Page 1

... PIC24FJXXXGA0XX family. Customers using only one of these devices should use development tools that already provide support for device programming. This specification includes programming specifications for the following devices: • PIC24FJ16GA002 • PIC24FJ96GA006 • PIC24FJ16GA004 • PIC24FJ96GA008 • PIC24FJ32GA002 • PIC24FJ96GA010 • PIC24FJ32GA004 • PIC24FJ128GA006 • ...

Page 2

... Timing Requirements” for the full operating ranges of V CONNECTIONS FOR THE ON-CHIP REGULATOR (28/44-PIN DEVICES 3.3V PIC24FJXXXGA0XX V DD DISVREG V /V DDCORE CAP (1) 3.3V PIC24FJXXXGA0XX V DD DISVREG V /V DDCORE CAP V SS tied DDCORE PIC24FJXXXGA0XX V DD DISVREG V /V DDCORE CAP V SS and DDCORE © 2008 Microchip Technology Inc. ...

Page 3

... Applies to 28 and 44-pin devices only. 2: All power supply and ground pins must be connected, including analog supplies (AV ( © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX 2.3 Pin Diagrams The pin diagrams for the PIC24FJXXXGA0XX family are shown in the following figures. The pins that are required for programming are listed in Table 2-1 and are shown in bold letters in the figures ...

Page 4

... PGD2/EMUD2/TDI/RP10/CN16/PMD2/RB10 CAP DDCORE RA2 9 20 DISVREG 10 19 RA3 RB9 11 18 RB4 RB8 12 17 RA4 13 16 RB7 PGC3/EMUC3/RP6/SCL1/CN24/PMD6/RB6 RB13 2 20 RB12 RB2 3 19 PGC2/EMUC2/TMS/RP11/CN15/PMD1/RB11 PIC24FJXXGA002 RB3 4 18 PGD2/EMUD2/TDI/RP10/CN16/PMD2/RB10 CAP DDCORE RA2 6 16 DISVREG RA3 7 15 RB9 © 2008 Microchip Technology Inc. ...

Page 5

... Pin Diagrams (Continued) (1) 44-Pin QFN PGD2/EMUD2/RP10/CN16/PMD2/RB10 PGC2/EMUC2/RP11/CN15/PMD1/RB11 Legend: RPx represents remappable peripheral pins. Note 1: The bottom pad of QFN packages should be connected to V © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX 33 RB9 1 32 RC6 2 31 RC7 3 30 RC8 4 29 RC9 5 PIC24FJXXGA004 28 DISVREG CAP DDCORE ...

Page 6

... Pin Diagrams (Continued) 44-Pin TQFP PGD2/EMUD2/RP10/CN16/PMD2/RB10 PGC2/EMUC2/RP11/CN15/PMD1/RB11 Legend: RPx represents remappable peripheral pins. DS39768D-page 6 RB9 1 RC6 2 RC7 3 RC8 4 RC9 5 PIC24FJXXGA004 DISVREG CAP DDCORE 8 9 RB12 10 RB13 11 33 RB4 32 RA8 31 RA3 30 RA2 RC2 26 RC1 25 RC0 24 RB3 23 RB2 © 2008 Microchip Technology Inc. ...

Page 7

... Pin Diagrams (Continued) 64-Pin TQFP PGC1/EMUC1/V -/AN1/CN3/RB1 REF PGD1/EMUD1/PMA6/V +/AN0/CN2/RB0 REF © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX 1 RE5 RE6 2 RE7 3 RG6 4 RG7 5 RG8 6 MCLR 7 PIC24FJXXGA006 RG9 8 PIC24FJXXXGA006 RB5 11 RB4 12 RB3 13 RB2 RC14 47 RC13 46 RD0 45 RD11 44 RD10 43 RD9 42 RD8 41 Vss 40 RC15 39 RC12 ...

Page 8

... RC1 RC3 RG6 RG7 RG8 MCLR RG9 RE8 RE9 RB5 RB4 RB3 RB2 PGC1/EMUC1/AN1/CN3/RB1 PGD1/EMUD1/AN0/CN2/RB0 DS39768D-page PIC24FJXXGA008 10 PIC24FJXXXGA008 RC14 59 RC13 58 RD0 57 RD11 56 RD10 55 RD9 54 RD8 53 RA15 52 RA14 RC15 49 RC12 RG2 46 RG3 45 RF6 44 RF7 43 RF8 42 RF2 41 RF3 © 2008 Microchip Technology Inc. ...

Page 9

... Pin Diagrams (Continued) 100-Pin TQFP RG15 V DD RE5 RE6 RE7 RC1 RC2 RC3 RC4 RG6 RG7 RG8 MCLR PRG9 RA0 RE8 RE9 RB5 RB4 RB3 RB2 PGC1/EMUC1/AN1/CN3/RB1 PGD1/EMUD1/AN0/CN2/RB0 © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX PIC24FJXXGA010 13 PIC24FJXXXGA010 RC14 74 73 RC13 RD0 72 71 ...

Page 10

... CODE MEMORY SIZE User Memory Write Erase Address Limit Blocks Blocks (Instruction Words) 002BFEh (5.5K 0057FEh (11K) 176 22 0083FEh (16.5K) 264 33 00ABFEh (22K) 344 43 00FFFEh (32K) 512 64 0157FEh (44K) 688 86 © 2008 Microchip Technology Inc. ...

Page 11

... FIGURE 2-4: PROGRAM MEMORY MAP Note 1: The address boundaries for user Flash code memory are device dependent (see Table 2-3). © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX 000000h User Flash Code Memory (44031 x 24-bit) (1) 0157FAh (1) 0157FCh Configuration Words ( 24-bit) 0157FEh (1) 015800h Reserved ...

Page 12

... VISI register. TABLE 3-1: CPU CONTROL CODES IN ICSP™ MODE 4-Bit Mnemonic Description Control Code SIX Shift in 24-bit instruction 0000b and execute. REGOUT Shift out the VISI (0784h) 0001b register. 0010b-1111b N/A Reserved. © 2008 Microchip Technology Inc. ...

Page 13

... A CPU stall occurs when an instruction modifies a register that is used for Indirect Addressing by the following instruction. © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX Coming out of Reset, the first 4-bit control code is always forced to SIX and a forced NOP instruction is executed by the CPU. Five additional PGCx clocks are needed on start-up, resulting in a 9-bit SIX command instead of the normal 4-bit SIX command ...

Page 14

... PGCx. For all Significant bit (LSb) is transmitted first ... LSb Shift Out VISI Register<15:0> PGDx = Output PIC24FJXXXGA0XX device data transmissions, the Least P4A MSb Execution Takes Place, Fetch Next Control Code PGDx = Input © 2008 Microchip Technology Inc. ...

Page 15

... PGDx b31 b30 PGCx P18 © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX The key sequence is a specific 32-bit pattern: ‘0100 1101 0100 0011 0100 1000 0101 0001’ (more easily remembered as 4D434851h in hexa- decimal). The device will enter Program/Verify mode only if the sequence is valid. The Most Significant bit (MSb) of the most significant nibble must be shifted in first ...

Page 16

... PGCx and PGDx pins (see Figure 3-2). Note: Program memory must be erased before writing any data to program memory. FIGURE 3-5: CHIP ERASE FLOW Start Write 404Fh to NVMCON SFR Set the WR bit to Initiate Erase Delay P11 + P10 Time Done © 2008 Microchip Technology Inc. ...

Page 17

... MOV 0000 883C22 MOV 0000 000000 NOP 0001 <VISI> Clock out contents of the VISI register. 0000 000000 NOP © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX Description 0x200 #0x404F, W10 W10, NVMCON #<PAGEVAL>, W0 W0, TBLPAG #0x0000, W0 W0,[W0] NVMCON, #WR 0x200 NVMCON, W2 W2, VISI ...

Page 18

... Steps 3-9 are repeated until all of code memory is programmed. FIGURE 3- MSB1 MSB3 W5 Description 0x200 #0x4001, W10 W10, NVMCON #<DestinationAddress23:16>, W0 W0, TBLPAG #<DestinationAddress15:0>, W7 #<LSW0>, W0 #<MSB1:MSB0>, W1 #<LSW1>, W2 #<LSW2>, W3 #<MSB3:MSB2>, W4 #<LSW3>, W5 PACKED INSTRUCTION WORDS IN W<0:5> LSW0 MSB0 LSW1 LSW2 MSB2 LSW3 © 2008 Microchip Technology Inc. ...

Page 19

... Clock out contents of the VISI register. 0000 000000 NOP Step 9: Reset device internal PC. 0000 040200 GOTO 0000 000000 NOP Step 10: Repeat Steps 3-9 until all code memory is programmed. © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX Description W6 [W6++], [W7] [W6++], [W7++] [W6++], [W7] [W6++], [W7++] NVMCON, #WR 0x200 NVMCON, W2 W2, VISI ...

Page 20

... PROGRAM CODE MEMORY FLOW LoopCount = LoopCount + 1 DS39768D-page 20 Start LoopCount = 0 Configure Device for Writes Load 2 Bytes to Write Buffer at <Addr> All No bytes written? Yes Start Write Sequence and Poll for WR bit to be Cleared All No locations done? Yes Done © 2008 Microchip Technology Inc. ...

Page 21

... ICSP command code which must be transmitted, Least Significant bit first, using the PGCx and PGDx pins (see Figure 3-2). © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX In Step 1, the Reset vector is exited. In Step 2, the NVMCON register is initialized for programming of code memory ...

Page 22

... NOP Step 9: Reset device internal PC. 0000 040200 GOTO 0000 000000 NOP Step 10: Repeat Steps 5-9 to write CW1. DS39768D-page 22 Description 0x200 <CW2Address15:0>, W7 #0x4003, W10 W10, NVMCON <CW2Address23:16>, W0 W0, TBLPAG #<CW2_VALUE>, W6 W6, [W7++] NVMCON, #WR 0x200 NVMCON, W2 W2, VISI 0x200 © 2008 Microchip Technology Inc. ...

Page 23

... NOP Step 6: Repeat Steps 4 and 5 until all desired code memory is read. © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX To minimize the reading time, the packed instruction word format that was utilized for writing is also used for reading (see Figure 3-6). In Step 3, the Write Pointer, W7, is initialized ...

Page 24

... Kbyte devices (the upper byte address of configuration memory), and the Read Pointer, W6, is initialized to the lower 16 bits of the Configuration Word location. Description 0x200 <CW2Address23:16>, W0 W0, TBLPAG <CW2Address15:0>, W6 #VISI, W7 [W6++], [W7] 0x200 © 2008 Microchip Technology Inc. ...

Page 25

... Yes All No code memory verified? Yes Done © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX 3.11 Reading the Application ID Word The Application ID Word is stored at address 8005BEh in executive code memory. To read this memory location, you must use the SIX control code to move this program memory location to the VISI register. ...

Page 26

... TBLRDL 0000 000000 NOP 0000 000000 NOP Step 3: Output the VISI register using the REGOUT command. 0001 <VISI> Clock out contents of the VISI register 0000 000000 NOP DS39768D-page 26 Description 0x200 #0x80, W0 W0, TBLPAG #0x5BE, W0 #VISI, W1 [W0], [W1] © 2008 Microchip Technology Inc. ...

Page 27

... Next, the device is erased. Then, the code memory is programmed, followed by the configuration locations. Code memory (including the Configuration registers) is then verified to ensure that programming was successful. © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX After the programming executive has been verified in memory (or ...

Page 28

... On successful entry, the program memory can be accessed and programmed in serial fashion. While in the Program/Verify mode, all unused I/Os are placed in the high-impedance state Program/Verify Entry Code = 4D434850h ... 0 b31 b30 b29 b28 b27 b3 P1A P1B , the case After must be IH P19 © 2008 Microchip Technology Inc. ...

Page 29

... On the second PROGP command, the second row is programmed. This process is repeated until the entire device is programmed. No special handling must be performed when a panel boundary is crossed. © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX FIGURE 4-4: BaseAddress = BaseAddress + 80h ...

Page 30

... General Segment Code-Protect bit 1 = User program memory is not code-protected 0 = User program memory is code-protected General Segment Write-Protect bit 1 = User program memory is not write-protected 0 = User program memory is write-protected ICD Communication Channel Select bit 1 = Communicate on PGC2/EMUC2 and PGD2/EMUD2 0 = Communicate on PGC1/EMUC1 and PGD1/EMUD1 © 2008 Microchip Technology Inc. ...

Page 31

... WUTSEL0 Note 1: Available on 28 and 44-pin packages only. 2: Available only on 28 and 44-pin devices with a silicon revision of 3042h or higher. © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX Description ICD Pin Placement Select bit 11 = ICD EMUC/EMUD pins are shared with PGC1/PGD1 10 = ICD EMUC/EMUD pins are shared with PGC2/PGD2 01 = ICD EMUC/EMUD pins are shared with PGC3/PGD3 00 = Reserved ...

Page 32

... GWRP or GCP be programmed to ‘0’ (see Section 4.6 “Configuration Bits Programming”). Note: Bulk Erasing in ICSP mode is the only way to reprogram code-protect bits from an ON state (‘0’ Off state (‘1’). © 2008 Microchip Technology Inc. ...

Page 33

... Exiting Program/Verify mode is done by removing V from MCLR, as shown in Figure 4-6. The only require- ment for exit is that an interval, P16, should elapse between the last clock and program signals on PGCx and PGDx before removing © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX Start ConfigAddress = 0157FCh Send PROGW Command Is ...

Page 34

... As a safety measure, the programmer should use the command time-outs identified in Table 5-1. If the command time-out expires, the programmer should reset the programming programming the device again. PROGRAMMING EXECUTIVE SERIAL TIMING FOR DATA TRANSMITTED TO DEVICE ... LSb executive and start © 2008 Microchip Technology Inc. ...

Page 35

... SPI port. If the value of this field is incorrect, the command will not be properly received by the programming executive. © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX Programming Executive Host Clocks Out Response Processes Command ...

Page 36

... This command is used as a “Sanity Check” to verify that the programming executive is operational. Expected Response (2 words): 1000h 0002h 0 Note: This instruction is not required for programming development purposes only. but is provided for © 2008 Microchip Technology Inc. ...

Page 37

... Expected Response ( – 1)/2 words for N odd): 1100h Device ID Register 1 ... Device ID Register N Note: Reading unimplemented memory will cause the programming executive to reset. Please ensure that only memory locations present on a particular device are accessed. © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX 5.2.7 READP COMMAND Opcode N Reserved Addr_LS ...

Page 38

... After all data has been programmed to code memory, the programming executive verifies the programmed data against the data in the command. Expected Response (2 words): 1500h 0002h Note: Refer to Table 2-3 for code memory size information. © 2008 Microchip Technology Inc. 0 Length Addr_MSB Description ...

Page 39

... After the word has been programmed to code memory, the programming executive verifies the programmed data against the data in the command. Expected Response (2 words): 1600h 0002h © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX 5.2.11 QBLANK COMMAND Opcode ...

Page 40

... Since the program- ming executive can only process one command at a time, this field is technically not required. However, it can be used to verify that the programming executive correctly received the command that the programmer transmitted. © 2008 Microchip Technology Inc. 0 QE_Code Description ...

Page 41

... If the verify of the programming for the PROGP or PROGC command fails, the QE_Code is set to 1h. For all other programming executive errors, the QE_Code is 2h. © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX TABLE 5-4: QE_Code FOR NON-QUERY COMMANDS ...

Page 42

... This control flow is summarized in Table 5-5. Description 0x200 #0x80, W0 W0, TBLPAG #0x07F0, W1 #0xC, W2 [W1++].[W2++] #0x4042, W0 W0, NVMCON #0x80, W0 W0, TBLPAG #0x0, W1 W1, [W1] NVMCON, #15 0x200 NVMCON, W2 W2, VISI © 2008 Microchip Technology Inc. ...

Page 43

... MOV 0000 2<MSB1:MSB0>1 MOV 0000 2<LSW1>2 MOV 0000 2<LSW2>3 MOV 0000 2<MSB3:MSB2>4 MOV 0000 2<LSW3>5 MOV © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX Description #0x80, W0 W0, TBLPAG #0x4003, W1 W1, NVMCON #0x07F0, W1 #0xC, W2 [W2++], [W1++] NVMCON, #15 0x200 NVMCON, W0 W0, VISI #0x4001, W0 W0, NVMCON #0x80, W0 ...

Page 44

... Step 20: Repeat Steps 14-19 until all 16 rows of executive memory have been programmed. On the final row, make sure to initialize the write latches at the Diagnostic and Calibration Words locations with 0xFFFFFF to ensure that the calibration is not overwritten. DS39768D-page 44 Description W6 [W6++], [W7] [W6++], [W7++] [W6++], [W7] [W6++], [W7++] NVMCON, #15 0x200 NVMCON, W2 W2, VISI 0x200 © 2008 Microchip Technology Inc. ...

Page 45

... GOTO 0000 000000 NOP Step 6: Repeat Steps 4 and 5 until all desired code memory is read. © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX Reading the contents of executive memory can be performed using the same technique described in has been Section 3.8 “Reading Code Memory”. A procedure for reading executive memory is shown in Table 5-6 ...

Page 46

... DEVID FF0002h DEVREV TABLE 6-3: DEVICE ID BIT DESCRIPTIONS Bit Field Register FAMID<7:0> DEVID DEV<5:0> DEVID MAJRV<2:0> DEVREV DOT<2:0> DEVREV DS39768D-page 46 TABLE 6-1: Device PIC24FJ16GA002 PIC24FJ16GA004 manufacturing PIC24FJ32GA002 PIC24FJ32GA004 PIC24FJ48GA002 PIC24FJ48GA004 PIC24FJ64GA002 PIC24FJ64GA004 PIC24FJ64GA006 PIC24FJ64GA008 PIC24FJ64GA010 PIC24FJ96GA006 PIC24FJ96GA008 PIC24FJ96GA010 PIC24FJ128GAGA006 PIC24FJ128GAGA008 PIC24FJ128GAGA010 ...

Page 47

... Checksums for the PIC24FJXXXGA0XX family are 16 bits in size. The checksum is calculated by summing the following: • Contents of code memory locations • Contents of Configuration registers TABLE 6-4: CHECKSUM COMPUTATION Read Code Device Protection Disabled PIC24FJ16GA002 Enabled Disabled PIC24FJ16GA004 Enabled Disabled PIC24FJ32GA002 Enabled Disabled PIC24FJ32GA004 Enabled ...

Page 48

... CW1 address is last location of implemented program memory; CW2 is (last location – 2). DS39768D-page 48 Erased Checksum Computation Checksum Value CFGB + SUM(0:0157FB) 0xF8CC 0 0x0000 CFGB + SUM(0:0157FB) 0xF8CC 0 0x0000 CFGB + SUM(0:0157FB) 0xF8CC 0 0x0000 Checksum with 0xAAAAAA at 0x0 and Last Code Address 0xF6CE 0x0000 0xF6CE 0x0000 0xF6CE 0x0000 © 2008 Microchip Technology Inc. ...

Page 49

... Delay Between Programming Executive DLY Command Response Words Note 1: V must be supplied to the V DDCORE “Power Requirements” for more information. (Minimum must also be supplied to the and V , respectively © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX Min Max V + 0.1 3.60 DDCORE — 5 — 0 0.8 V ...

Page 50

... PIC24FJXXXGA0XX NOTES: DS39768D-page 50 © 2008 Microchip Technology Inc. ...

Page 51

... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 52

... Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2008 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...

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