PIC24FJ16GA002-E/ML Microchip Technology, PIC24FJ16GA002-E/ML Datasheet

IC PIC MCU FLASH 16K 28-QFN

PIC24FJ16GA002-E/ML

Manufacturer Part Number
PIC24FJ16GA002-E/ML
Description
IC PIC MCU FLASH 16K 28-QFN
Manufacturer
Microchip Technology
Series
PIC® 24Fr

Specifications of PIC24FJ16GA002-E/ML

Program Memory Type
FLASH
Program Memory Size
16KB (5.5K x 24)
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
21
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
21
Number Of Timers
5
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, MA240013, AC164127, DM300027, DV164033, DM240002
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24FJ16GA002-E/ML
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
PIC24FJ16GA002-E/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC24FJ64GA004 Family
Data Sheet
28/44-Pin General Purpose,
16-Bit Flash Microcontrollers
 2010 Microchip Technology Inc.
DS39881D

Related parts for PIC24FJ16GA002-E/ML

PIC24FJ16GA002-E/ML Summary of contents

Page 1

... PIC24FJ64GA004 Family  2010 Microchip Technology Inc. Data Sheet 28/44-Pin General Purpose, 16-Bit Flash Microcontrollers DS39881D ...

Page 2

... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 3

... Microchip Technology Inc. PIC24FJ64GA004 FAMILY Analog Features: • 10-Bit 13-Channel Analog-to-Digital Converter: - 500 ksps conversion rate - Conversion available during Sleep and Idle • Dual Analog Comparators with Programmable Input/Output Configuration Peripheral Features: • Peripheral Pin Select: ...

Page 4

... SS AN9/RP15/CN11/PMCS1/RB15 3 26 -/CN3/RA1 AN10/CV /RTCC/RP14/CN12/PMWR/RB14 4 25 REF AN11/RP13/CN13/PMRD/RB13 5 24 AN12/RP12/CN14/PMD0/RB12 6 23 PGC2/EMUC2/TMS/RP11/CN15/PMD1/RB11 7 22 PGD2/EMUD2/TDI/RP10/CN16/PMD2/RB10 CAP DDCORE DISVREG 10 19 TDO/RP9/SDA1/CN21/PMD3/RB9 11 18 TCK/RP8/SCL1/CN22/PMD4/RB8 RP7/INT0/CN23/PMD5/RB7 PGC3/EMUC3/RP6/ASCL1/CN24/PMD6/RB6 AN11/RP13/CN13/PMRD/RB13 2 AN12/RP12/CN14/PMD0/RB12 PGC2/EMUC2/TMS/RP11/CN15/PMD1/RB11 PIC24FJXXGA002 4 18 PGD2/EMUD2/TDI/RP10/CN16/PMD2/RB10 CAP DDCORE 6 16 DISVREG 7 15 TDO/RP9/SDA1/CN21/PMD3/RB9  2010 Microchip Technology Inc. ...

Page 5

... Pin Diagrams (Continued) (1) 44-Pin QFN RP9/SDA1/CN21/PMD3/RB9 RP22/CN18/PMA1/RC6 RP23/CN17/PMA0/RC7 RP24/CN20/PMA5/RC8 RP25/CN19/PMA6/RC9 DISVREG V CAP PGD2/EMUD2/RP10/CN16/PMD2/RB10 PGC2/EMUC2/RP11/CN15/PMD1/RB11 AN12/RP12/CN14/PMD0/RB12 AN11/RP13/CN13/PMRD/RB13 RPn represents remappable peripheral pins. Legend: Back pad on QFN devices should be connected to Vss. Note 1:  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 33 SOSCI/RP4/CN1/RB4 1 TDO/PMA8/RA8 OSCO/CLKO/CN29/RA3 3 30 OSCI/CLKI/CN30/RA2 ...

Page 6

... RP23/CN17/PMA0/RC7 RP24/CN20/PMA5/RC8 RP25/CN19/PMA6/RC9 DISVREG V /V CAP DDCORE PGD2/EMUD2/RP10/CN16/PMD2/RB10 PGC2/EMUC2/RP11/CN15/PMD1/RB11 AN12/RP12/CN14/PMD0/RB12 AN11/RP13/CN13/PMRD/RB13 RPn represents remappable peripheral pins. Legend: DS39881D-page SOSCI/RP4/CN1/RB4 32 TDO/PMA8/RA8 2 31 OSCO/CLKO/CN29/RA3 3 30 OSCI/CLKI/CN30/RA2 PIC24FJXXGA004 AN8/RP18/CN10/PMA2/RC2 7 26 AN7/RP17/CN9/RC1 8 25 AN6/RP16/CN8/RC0 9 24 AN5/C1IN+/RP3/SCL2/CN7/RB3 10 AN4/C1IN-/RP2/SDA2/CN6/RB2 23 11  2010 Microchip Technology Inc. ...

Page 7

... Appendix A: Revision History............................................................................................................................................................. 259 Appendix B: Additional Guidance for PIC24FJ64GA004 Family Applications ................................................................................... 260 Index ................................................................................................................................................................................................. 261 The Microchip Web Site ..................................................................................................................................................................... 265 Customer Change Notification Service .............................................................................................................................................. 265 Customer Support .............................................................................................................................................................................. 265 Reader Response .............................................................................................................................................................................. 266 Product Identification System ............................................................................................................................................................ 267  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY DS39881D-page 7 ...

Page 8

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39881D-page 8  2010 Microchip Technology Inc. ...

Page 9

... DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC24FJ16GA002 • PIC24FJ32GA002 • PIC24FJ48GA002 • PIC24FJ64GA002 • PIC24FJ16GA004 • PIC24FJ32GA004 • PIC24FJ48GA004 • PIC24FJ64GA004 This family introduces a new line of Microchip devices: a 16-bit microcontroller family with a broad peripheral feature set and enhanced computational performance ...

Page 10

... Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first. memory (64 Kbytes for devices, 48 Kbytes for devices, 32 Kbytes for features available on the  2010 Microchip Technology Inc. ...

Page 11

... JTAG Boundary Scan 10-Bit Analog-to-Digital Module (input channels) Analog Comparators Remappable Pins Resets (and delays) Instruction Set Packages Peripherals are accessible through remappable pins. Note 1:  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY DC – 32 MHz 16K 32K 48K 64K 5,504 11,008 16,512 ...

Page 12

... Inst Register Divide Control Signals Support Reg Array 17x17 Multiplier (2) MCLR 10-Bit RTCC (3) (3) Timer4/5 ADC (1) (3) I2C1/2 CN1-22 SPI1/2 (3) 16 (1) PORTA RA0:RA9 16 16 PORTB RB0:RB15 16 PORTC (1) 16 RC0:RC9 RP (1) RP0:RP25 16-Bit ALU 16 Comparators (3) PMP/PSP (3) UART1/2  2010 Microchip Technology Inc. ...

Page 13

... C2IN CLKI 9 6 CLKO 10 7 TTL = TTL input buffer Legend: ANA = Analog level input/output Alternative multiplexing when the I2C1SEL Configuration bit is cleared. Note 1:  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Input I/O 44-Pin Buffer 19 I ANA A/D Analog Inputs ANA 21 I ANA ...

Page 14

... In-Circuit Emulator Data Input/Output. 42 I/O ST In-Circuit Emulator Clock Input/Output. 41 I/O ST In-Circuit Emulator Data Input/Output External Interrupt Input Master Clear (device Reset) Input. This line is brought low to cause a Reset Schmitt Trigger input buffer C™ C/SMBus input buffer Description  2010 Microchip Technology Inc. ...

Page 15

... PMRD 24 21 PMWR 25 22 TTL = TTL input buffer Legend: ANA = Analog level input/output Alternative multiplexing when the I2C1SEL Configuration bit is cleared. Note 1:  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Input I/O 44-Pin Buffer 30 I ANA Main Oscillator Input Connection ANA Main Oscillator Output Connection ...

Page 16

... PORTA Digital I/ I/O ST PORTB Digital I/ I/O ST PORTC Digital I/ Schmitt Trigger input buffer C™ C/SMBus input buffer Description  2010 Microchip Technology Inc. ...

Page 17

... SDA2 6 3 SOSCI 11 8 SOSCO 12 9 TTL = TTL input buffer Legend: ANA = Analog level input/output Alternative multiplexing when the I2C1SEL Configuration bit is cleared. Note 1:  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Input I/O 44-Pin Buffer 21 I/O ST Remappable Peripheral I/O ST ...

Page 18

... Positive Supply for Microcontroller Core Logic (regulator disabled ANA A/D and Comparator Reference Voltage (low) Input ANA A/D and Comparator Reference Voltage (high) Input. 29 — Ground Reference for Logic and I/O Pins Schmitt Trigger input buffer C™ C/SMBus input buffer Description  2010 Microchip Technology Inc. ...

Page 19

... REF REF reference for analog modules is implemented The AV and AV pins must always be Note connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure 2-1.  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY FIGURE 2- MCLR (2) C6 ...

Page 20

... The DD may be beneficial. A typical ) and fast signal transitions must IL is replaced for normal run-time EXAMPLE OF MCLR PIN CONNECTIONS R1 R2 MCLR PIC24FXXXX JP C1 and V specifications are met and V specifications are met. IL  2010 Microchip Technology Inc. ...

Page 21

... When the regulator is disabled, the V CAP must be tied to a voltage supply at the V Refer to Section 27.0 “Electrical Characteristics” for information on V and DDCORE  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY FIGURE 2- 0.1 0.01 0.001 0.01 Data for Murata GRM21BF50J106ZE01 shown. ...

Page 22

... Copper Pour (tied to ground) OSCO GND Devices” OSCI DEVICE PINS SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Primary Oscillator Crystal DEVICE PINS OSCI ` OSCO GND ` SOSCO SOSC I ` Sec Oscillator: C2 Top Layer Copper Pour (tied to ground) C2 Oscillator Crystal C1  2010 Microchip Technology Inc. ...

Page 23

... Microchip Technology Inc. PIC24FJ64GA004 FAMILY If your application needs to use certain A/D pins as analog input pins during the debug session, the user application must modify the appropriate bits during initialization of the ADC module, as follows: • ...

Page 24

... PIC24FJ64GA004 FAMILY NOTES: DS39881D-page 24  2010 Microchip Technology Inc. ...

Page 25

... Register Indirect modes. Each group offers up to seven addressing modes. Instructions are associated with predefined addressing modes depending upon their functional requirements.  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY For most instructions, the core is capable of executing a data (or program data) memory read, a working reg- ister (data) read, a data memory write and a program (instruction) memory read per instruction cycle ...

Page 26

... Decode & Control Control Signals to Various Blocks DS39881D-page 26 Data Bus Data Latch PCL Data RAM Address Loop Latch Control Logic 16 RAGU WAGU EA MUX ROM Latch 16 Instruction Reg Hardware Multiplier Register Array Divide Support 16-Bit ALU Peripheral Modules  2010 Microchip Technology Inc. ...

Page 27

... W10 W11 W12 W13 W14 W15 22 Registers or bits shadowed for PUSH.S and POP.S instructions.  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Description Working Register Array 23-Bit Program Counter ALU STATUS Register Stack Pointer Limit Value Register Table Memory Page Address Register ...

Page 28

... Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1. DS39881D-page 28 U-0 U-0 — — (1) R-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1,2) U-0 U-0 R/W-0 — — DC bit 8 R/W-0 R/W-0 R/W bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 29

... Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location.  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — ...

Page 30

... All multi-bit shift instructions only support Register Direct Addressing for both the operand source and result destination. A full summary of instructions that use the shift operation is provided below in Table 3-2. Description  2010 Microchip Technology Inc. ...

Page 31

... Device Config Registers Reserved DEVID (2) Memory areas are not shown to scale. Note:  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY from either the 23-bit Program Counter (PC) during pro- gram execution, or from table operation or data space remapping, as described in Section 4.3 “Interfacing Program and Data Memory Spaces”. ...

Page 32

... PIC24FJ48GA PIC24FJ64GA least significant word Instruction Width FLASH CONFIGURATION WORDS FOR PIC24FJ64GA004 FAMILY DEVICES Program Configuration Memory Word (K words) Addresses 002BFCh: 5.5 002BFEh 0057FCh: 11 0057FEh 0083FCh: 16 0083FEh 00ABFCh: 22 00ABFEh PC Address (lsw Address) 0 000000h 000002h 000004h 000006h  2010 Microchip Technology Inc. ...

Page 33

... Data memory areas are not shown to scale. Note 1: Upper memory limit for PIC24FJ16GAXXX devices is 17FFh. 2:  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY PIC24FJ64GA family devices implement a total of 8 Kbytes of data memory. Should an EA point to a location outside of this area, an all zero word or byte will be returned ...

Page 34

... CRC — System NVM/PMD — xxA0 xxC0 xxE0 Interrupts — — — — — I/O — — — — — — — — — PPS — — —  2010 Microchip Technology Inc. ...

Page 35

TABLE 4-3: CPU CORE REGISTERS MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 ...

Page 36

TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name INTCON1 0080 NSTDIS — — — INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 U2TXIF U2RXIF INT2IF ...

Page 37

TABLE 4-6: TIMER REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — ...

Page 38

TABLE 4-8: OUTPUT COMPARE REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — OC3RS 018C OC3R ...

Page 39

TABLE 4-10: UART REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name U1MODE 0220 UARTEN — USIDL IREN U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — U1TXREG 0224 — — — — U1RXREG 0226 — — — — ...

Page 40

TABLE 4-12: PORTA REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name TRISA 02C0 — — — — PORTA 02C2 — — — — LATA 02C4 — — — — ODCA 02C6 — — — — ...

Page 41

TABLE 4-16: ADC REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ...

Page 42

TABLE 4-18: REAL-TIME CLOCK AND CALENDAR REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name ALRMVAL 0620 ALCFGRPT 0622 ALRMEN CHIME AMASK3 AMASK2 RTCVAL 0624 RCFGCAL 0626 RTCEN — RTCWREN RTCSYNC HALFSEC — = unimplemented, read ...

Page 43

TABLE 4-21: PERIPHERAL PIN SELECT REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPINR0 0680 — — — INT1R4 RPINR1 0682 — — — — RPINR3 0686 — — — T3CKR4 RPINR4 0688 — — ...

Page 44

TABLE 4-22: CLOCK CONTROL REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RCON 0740 TRAPR IOPUWR — — OSCCON 0742 — COSC2 COSC1 COSC0 CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 OSCTUN 0748 — — — ...

Page 45

... W15 (before CALL) PC<22:16> 000000000 <Free Word> W15 (after CALL) POP : [--W15] PUSH : [W15++]  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 4.3 Interfacing Program and Data Memory Spaces The PIC24F architecture uses a 24-bit wide program space and 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space ...

Page 46

... Bits 24 Bits Select 1 PSVPAG 0 8 Bits 23 Bits <15> <14:1> <0> PC<22:1> 0 Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<15:0> xxxx xxxx xxxx xxxx (1) Data EA<14:0> xxx xxxx xxxx xxxx 0 EA 1/0 16 Bits Bits Byte Select  2010 Microchip Technology Inc. ...

Page 47

... FIGURE 4-6: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 2. TBLRDH (Table Read High): In Word mode, it maps the entire upper word of a program address (P<23:16> data address. Note that D<15:8>, the ‘phantom’ byte, will always be ‘0’. ...

Page 48

... PSV Area 800000h 1111’ or 0000h Data EA<14:0> 8000h ...while the lower 15 bits of the EA specify an exact address within the PSV area. FFFFh This corresponds exactly to the same lower 15 bits of the actual program space address.  2010 Microchip Technology Inc. ...

Page 49

... Using Table Instruction User/Configuration Space Select  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may write program memory data in blocks of 64 instruc- tions (192 bytes time, and erase program memory in blocks of 512 instructions (1536 bytes time. Manual” ...

Page 50

... Configuration Word values are stored in the last two locations of program memory. Performing a page erase operation on the last page of program memory clears these values and enables code protection result, avoid performing page erase operations on the last page of program memory.  2010 Microchip Technology Inc. ...

Page 51

... Memory page erase operation (ERASE = operation (ERASE = 0) 0001 = Memory row program operation (ERASE = operation (ERASE = 1) All other combinations of NVMOP3:NVMOP0 are unimplemented. Note 1: Available in ICSP™ mode only. Refer to device programming specification. 2:  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — ...

Page 52

... Initialize in-page EA[15:0] pointer ; Set base address of erase block ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted  2010 Microchip Technology Inc. ...

Page 53

... W0, NVMKEY MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP BTSC NVMCON, #15 BRA $-2  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY ; ; Initialize NVMCON ; ; Initialize PM Page Boundary SFR ; An example program memory address ; ; ; Write PM low word into program latch ; Write PM high byte into program latch ; ; ...

Page 54

... Write PM low word into program latch ; Write PM high byte into program latch ; ; Set NVMOP bits to 0011 ; Disable interrupts while the KEY sequence is written ; Write the key sequence ; Start the write cycle ; 2 NOPs required after setting WR ;  2010 Microchip Technology Inc. ...

Page 55

... Enable Voltage Regulator Trap Conflict Illegal Opcode Configuration Mismatch Uninitialized W Register  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. ...

Page 56

... SWDTEN bit setting. DS39881D-page 56 (1) U-0 U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) R/W-0 R/W-0 — CM VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 57

... BOR MCLR COSC Control bits (OSCCON<14:12>) WDTO SWR  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Setting Event 6.2 Device Reset Times The Reset times for various types of device Reset are summarized in Table 6-3. Note that the system Reset signal, SYSRST, is released after the POR and PWRT delay times expire ...

Page 58

... RST OST LOCK T — RST T — RST T — RST T — RST T — RST T — RST PWRT FSCM Notes Delay — FSCM FSCM FSCM — FSCM FSCM FSCM — 3 — 3 — 3 — 3 — 3 — 3 (64 ms nominal) if on-chip  2010 Microchip Technology Inc. ...

Page 59

... FRC oscillator and the user can switch to the desired crystal oscillator in the Trap Service Routine.  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 6.2.2.1 FSCM Delay for Crystal and PLL ...

Page 60

... PIC24FJ64GA004 FAMILY NOTES: DS39881D-page 60  2010 Microchip Technology Inc. ...

Page 61

... PIC24FJ64GA004 family devices non-maskable traps and unique interrupts. These are summarized in Table 7-1 and Table 7-2.  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 7.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 7-1. Access to the ...

Page 62

... Alternate Interrupt Vector Table (AIVT) 00017Ch 00017Eh 000180h 0001FEh 000200h AIVT Address 000104h Reserved 000106h Oscillator Failure 000108h Address Error 00010Ah Stack Error 00010Ch Math Error 00010Eh Reserved 000110h Reserved 0001172h Reserved (1) (1) Trap Source  2010 Microchip Technology Inc. ...

Page 63

... SPI2 Error SPI2 Event Timer1 Timer2 Timer3 Timer4 Timer5 UART1 Error UART1 Receiver UART1 Transmitter UART2 Error UART2 Receiver UART2 Transmitter LVD Low-Voltage Detect  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Vector AIVT IVT Address Number Address 13 00002Eh 00012Eh 18 000038h 000138h 67 ...

Page 64

... The CORCON register contains the IPL3 bit, which together with IPL2:IPL0, also indicates the current CPU priority level. IPL3 is a read-only bit so that trap events cannot be masked by the user software. All interrupt registers are described in Register 7-1 through Register 7-29, in the following pages.  2010 Microchip Technology Inc. ...

Page 65

... See Register 3-2 for the description of the remaining bit(s) that are not dedicated to interrupt control Note 1: functions. The IPL3 bit is concatenated with the IPL2:IPL0 bits (SR<7:5>) to form the CPU interrupt priority level. 2:  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — ...

Page 66

... Unimplemented: Read as ‘0’ DS39881D-page 66 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 MATHERR ADDRERR STKERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 U-0 OSCFAIL — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 67

... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — ...

Page 68

... Interrupt request has not occurred DS39881D-page 68 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF U-0 R/W-0 R/W-0 — T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPF1IF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 69

... MI2C1IF: Master I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 T5IF T4IF ...

Page 70

... Interrupt request has not occurred DS39881D-page 70 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared  2010 Microchip Technology Inc. R/W-0 U-0 OC5IF — bit 8 R/W-0 R/W-0 SPI2IF SPF2IF bit Bit is unknown ...

Page 71

... Interrupt request has not occurred bit 1 SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — — ...

Page 72

... Unimplemented: Read as ‘0’ DS39881D-page 72 U-0 U-0 U-0 — — — U-0 R/W-0 R/W-0 — CRCIF U2ERIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared  2010 Microchip Technology Inc. U-0 R/W-0 — LVDIF bit 8 R/W-0 U-0 U1ERIF — bit Bit is unknown ...

Page 73

... INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled If INTxIE = 1, this external interrupt input must be configured to an available RPn pin. See Section 10.4 Note 1: ”Peripheral Pin Select” for more information.  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 U1TXIE ...

Page 74

... Pin Select” for more information. DS39881D-page 74 R/W-0 R/W-0 (1) T5IE T4IE R/W-0 R/W-0 (1) INT1IE CNIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) R/W-0 R/W-0 U-0 OC4IE OC3IE — bit 8 R/W-0 R/W-0 R/W-0 CMIE MI2C1IE SI2C1IE bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 75

... SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — — ...

Page 76

... Unimplemented: Read as ‘0’ DS39881D-page 76 U-0 U-0 U-0 — — — U-0 U-0 R/W-0 — — MI2C2IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared  2010 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 U-0 SI2C2IE — bit Bit is unknown ...

Page 77

... U2ERIE: UART2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — — U-0 ...

Page 78

... Interrupt source is disabled DS39881D-page 78 R/W-0 U-0 R/W-1 T1IP0 — OC1IP2 R/W-0 U-0 R/W-1 IC1IP0 — INT0IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC1IP1 OC1IP0 bit 8 R/W-0 R/W-0 INT0IP1 INT0IP0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 79

... IC2IP2:IC2IP0: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 U-0 R/W-1 T2IP0 — OC2IP2 R/W-0 ...

Page 80

... Interrupt source is disabled DS39881D-page 80 R/W-0 U-0 R/W-1 U1RXIP0 — SPI1IP2 R/W-0 U-0 R/W-1 SPF1IP0 — T3IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPI1IP1 SPI1IP0 bit 8 R/W-0 R/W-0 T3IP1 T3IP0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 81

... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP2:U1TXIP0: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — — R/W-0 ...

Page 82

... Interrupt source is disabled DS39881D-page 82 R/W-0 U-0 R/W-1 CNIP0 — CMIP2 R/W-0 U-0 R/W-1 MI2C1P0 — SI2C1P2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 CMIP1 CMIP0 bit 8 R/W-0 R/W-0 SI2C1P1 SI2C1P0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 83

... Unimplemented: Read as ‘0’ bit 2-0 INT1IP2:INT1IP0: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — — U-0 ...

Page 84

... Unimplemented: Read as ‘0’ DS39881D-page 84 R/W-0 U-0 R/W-1 T4IP0 — OC4IP2 R/W-0 U-0 U-0 OC3IP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC4IP1 OC4IP0 bit 8 U-0 U-0 — — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 85

... Unimplemented: Read as ‘0’ bit 2-0 T5IP2:T5IP0: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 U-0 R/W-1 U2TXIP0 — U2RXIP2 R/W-0 ...

Page 86

... Interrupt source is disabled DS39881D-page 86 U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 SPI2IP0 — SPF2IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 SPF2IP1 SPF2IP0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 87

... IC3IP2:IC3IP0: Input Capture Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 U-0 R/W-1 IC5IP0 — IC4IP2 R/W-0 ...

Page 88

... PMPIP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 89

... SI2C2P2:SI2C2P0: Slave I2C2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 R/W-1 — — MI2C2P2 R/W-0 ...

Page 90

... Unimplemented: Read as ‘0’ DS39881D-page 90 U-0 U-0 R/W-1 — — RTCIP2 U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared  2010 Microchip Technology Inc. R/W-0 R/W-0 RTCIP1 RTCIP0 bit 8 U-0 U-0 — — bit Bit is unknown ...

Page 91

... U1ERIP2:U1ERIP0: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 U-0 R/W-1 CRCIP0 — U2ERIP2 R/W-0 ...

Page 92

... Interrupt source is disabled DS39881D-page 92 U-0 U-0 U-0 — — — U-0 U-0 R/W-1 — — LVDIP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared  2010 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 R/W-0 LVDIP1 LVDIP0 bit Bit is unknown ...

Page 93

... ISR will be re-entered immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level.  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 7.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, ...

Page 94

... PIC24FJ64GA004 FAMILY NOTES: DS39881D-page 94  2010 Microchip Technology Inc. ...

Page 95

... Secondary Oscillator SOSCO SOSCEN Enable SOSCI Oscillator  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY • Software-controllable switching between various clock sources • Software-controllable postscaler for selective clocking of CPU for system power savings • A Fail-Safe Clock Monitor (FSCM) that detects ...

Page 96

... Primary 00 Primary 10 Primary 01 Primary 00 Internal 11 Internal 11 the program memory (refer to for further “Configuration Bits” (Configuration Word 2<10:8>), Configuration bits (Configuration FNOSC2: Note FNOSC0 1, 2 111 1 110 1 101 1 100 011 011 010 010 010 1 001 1 000  2010 Microchip Technology Inc. ...

Page 97

... IOL1WAY Configuration bit is ‘1’ once the IOLOCK bit is set, it cannot be cleared. Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected. 3:  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY The Clock Divider register (Register 8-2) controls the features associated with Doze mode, as well as the postscaler for the FRC oscillator ...

Page 98

... The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed addition, if the IOL1WAY Configuration bit is ‘1’ once the IOLOCK bit is set, it cannot be cleared. Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected. 3: DS39881D-page 98 (2) (3)  2010 Microchip Technology Inc. ...

Page 99

... Unimplemented: Read as ‘0’ bit 6 Unimplemented: Read as ‘1’ bit 5-0 Unimplemented: Read as ‘0’ This bit is automatically cleared when the ROI bit is set and an interrupt occurs. Note 1:  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-1 R/W-0 R/W-0 (1) DOZE0 DOZEN ...

Page 100

... FNOSCx Configuration bits. The OSWEN control bit (OSCCON<0>) has no effect when clock switching is disabled held at ‘0’ at all times. U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 R/W-0 (1) (1) (1) TUN2 TUN1 TUN0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 101

... In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes.  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY A recommended code sequence for a clock switch includes the following: 1. Disable interrupts during the OSCCON register unlock and write sequence ...

Page 102

... Family Reference Manual”, Section 6. “Oscillator” (DS39700) and Microchip (CW2<12:11>), Application Notes: AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC Devices” (DS00826) and AN849, “Basic PICmicro Oscillator Design” (DS00849). ® ® and PICmicro ®  2010 Microchip Technology Inc. ...

Page 103

... Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY and code execution, but allows peripheral modules to continue operation. The assembly syntax of the PWRSAV instruction is shown in Example 9-1. Sleep and Idle modes can be exited as a result of an enabled interrupt, WDT time-out or a device Reset ...

Page 104

... By default, all modules that can operate during Idle mode will do so. Using the disable on Idle feature allows fur- ther reduction of power consumption during Idle mode, possible enhancing power savings for extremely critical power applications.  2010 Microchip Technology Inc. ...

Page 105

... CK WR PORT Data Latch Read LAT Read PORT  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled ...

Page 106

... Pull-ups on change notification pins Note: should always be disabled whenever the port pin is configured as a digital output. INPUT VOLTAGE LEVELS Tolerated Description Input V Only V input levels DD DD tolerated. (1) (1) 5.5V Tolerates input levels above V , useful for DD most standard logic. (1)  2010 Microchip Technology Inc. ...

Page 107

... I C™, change notification inputs, RTCC alarm outputs or peripherals with analog inputs.  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY A key difference between pin select and non pin select peripherals is that pin select peripherals are not asso- ciated with a default I/O pin. The peripheral must always be assigned to a specific I/O pin before it can be used ...

Page 108

... This permits any given pin to remain discon- nected from the output of any of the pin selectable peripherals. (1) Configuration Bits INTR1<4:0> INTR2R<4:0> T2CKR<4:0> T3CKR<4:0> T4CKR<4:0> T5CKR<4:0> IC1R<4:0> IC2R<4:0> IC3R<4:0> IC4R<4:0> IC5R<4:0> OCFAR<4:0> OCFBR<4:0> U1RXR<4:0> U1CTSR<4:0> U2RXR<4:0> U2CTSR<4:0> SDI1R<4:0> SCK1R<4:0> SS1R<4:0> SDI2R<4:0> SCK2R<4:0> SS2R<4:0>  2010 Microchip Technology Inc. ...

Page 109

... PIC24F devices include three features to prevent alterations to the peripheral map: • Control register lock sequence • Continuous state monitoring • Configuration bit remapping lock  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 10.4.4.1 Control Register Lock Under normal operation, writes to the RPINRx and RPORx registers are not allowed ...

Page 110

... Assign U1TX To Pin RP2 //*************************** RPOR1bits.RP2R = 3; //*************************** // Assign U1RTS To Pin RP3 //*************************** RPOR1bits.RP3R = 4; //************************************* // Lock Registers //************************************* asm volatile ( "MOV #OSCCON, w1 "MOV #0x46, w2 "MOV #0x57, w3 "MOV.b w2, [w1] "MOV.b w3, [w1] "BSET OSCCON, #6"  2010 Microchip Technology Inc. \n" \n" \n" \n" \n" \n" \n" \n" \n" \n" ); ...

Page 111

... Bit is set bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 INT2R4:INT2R0: Assign External Interrupt 2 (INT2) to the Corresponding RPn Pin bits  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Input and output register values can only Note: be changed if OSCCON<IOLOCK> See Section 10.4.4.1 “Control Register Lock” ...

Page 112

... T4CKR4 T4CKR3 T4CKR2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 T3CKR1 T3CKR0 bit 8 R/W-1 R/W-1 T2CKR1 T2CKR0 bit Bit is unknown R/W-1 R/W-1 T5CKR1 T5CKR0 bit 8 R/W-1 R/W-1 T4CKR1 T4CKR0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 113

... IC4R4:IC4R0: Assign Input Capture 4 (IC4) to the Corresponding RPn Pin bits bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 IC3R4:IC3R0: Assign Input Capture 3 (IC3) to the Corresponding RPn Pin bits  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-1 R/W-1 R/W-1 IC2R4 ...

Page 114

... OCFAR4 OCFAR3 OCFAR2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-1 R/W-1 IC5R1 IC5R0 bit Bit is unknown R/W-1 R/W-1 OCFBR1 OCFBR0 bit 8 R/W-1 R/W-1 OCFAR1 OCFAR0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 115

... U2CTSR4:U2CTSR0: Assign UART2 Clear to Send (U2CTS) to the Corresponding RPn Pin bits bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 U2RXR4:U2RXR0: Assign UART2 Receive (U2RX) to the Corresponding RPn Pin bits  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-1 R/W-1 R/W-1 U1CTSR4 ...

Page 116

... SS1R4 SS1R3 SS1R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 SCK1R1 SCK1R0 bit 8 R/W-1 R/W-1 SDI1R1 SDI1R0 bit Bit is unknown U-0 U-0 — — bit 8 R/W-1 R/W-1 SS1R1 SS1R0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 117

... W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 SS2R4:SS2R0: Assign SPI2 Slave Select Input (SS2IN) to the Corresponding RPn Pin bits  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-1 R/W-1 R/W-1 SCK2R4 SCK2R3 SCK2R2 ...

Page 118

... RP2R4 RP2R3 RP2R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 RP1R1 RP1R0 bit 8 R/W-0 R/W-0 RP0R1 RP0R0 bit Bit is unknown R/W-0 R/W-0 RP3R1 RP3R0 bit 8 R/W-0 R/W-0 RP2R1 RP2R0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 119

... Table 10-3 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP6R4:RP6R0: Peripheral Output Function is Assigned to RP6 Output Pin bits (see Table 10-3 for peripheral function numbers)  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 RP5R4 ...

Page 120

... RP10R4 RP10R3 RP10R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 RP9R1 RP9R0 bit 8 R/W-0 R/W-0 RP8R1 RP8R0 bit Bit is unknown R/W-0 R/W-0 RP11R1 RP11R0 bit 8 R/W-0 R/W-0 RP10R1 RP10R0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 121

... Table 10-3 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP14R4:RP14R0: Peripheral Output Function is Assigned to RP14 Output Pin bits (see Table 10-3 for peripheral function numbers)  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 RP13R4 ...

Page 122

... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 (1) (1) RP17R1 RP17R0 bit 8 R/W-0 R/W-0 (1) (1) RP16R1 RP16R0 bit Bit is unknown (1) (1) R/W-0 R/W-0 RP19R1 RP19R0 bit 8 R/W-0 R/W-0 RP18R1 RP18R0 bit Bit is unknown (1) (1)  2010 Microchip Technology Inc. ...

Page 123

... RP22R4:RP22R0: Peripheral Output Function is Assigned to RP22 Output Pin bits (see Table 10-3 for peripheral function numbers) Bits are only available on the 44-pin devices; otherwise, they read as ‘0’. Note 1:  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 ...

Page 124

... R/W-0 (1) (1) (1) RP25R4 RP25R3 RP25R2 R/W-0 R/W-0 R/W-0 (1) (1) (1) RP24R4 RP24R3 RP24R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 (1) (1) RP25R1 RP25R0 bit 8 R/W-0 R/W-0 (1) (1) RP24R1 RP24R0 bit Bit is unknown (1) (1)  2010 Microchip Technology Inc. ...

Page 125

... SOSCO/ T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Figure 11-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. Set the TON bit (= 1). 2. Select the timer prescaler ratio using the TCKPS1:TCKPS0 bits. ...

Page 126

... Unimplemented: Read as ‘0’ DS39881D-page 126 U-0 U-0 — — R/W-0 U-0 R/W-0 TCKPS0 — TSYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /2) U-0 U-0 U-0 — — — bit 8 R/W-0 U-0 TCS — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 127

... Timer2 and Timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 or Timer5 interrupt flags.  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. Set the T32 bit (T2CON<3> or T4CON<3> = 1). ...

Page 128

... Pin Select” for more information. The ADC event trigger is available only on Timer2/3. 3: DS39881D-page 128 1x Gate Sync PR3 PR2 (PR5) (PR4) Comparator LSB TMR2 TMR3 (TMR4) (TMR5 TMR3HLD (TMR5HLD) TCKPS1:TCKPS0 2 TON Prescaler 1, 8, 64, 256 (2) TGATE (2) TCS Sync  2010 Microchip Technology Inc. ...

Page 129

... Equal This peripheral’s inputs must be assigned to an available RPn pin before use. Please see Section Note 1: 10.4 “Peripheral Pin Select” for more information. The ADC event trigger is available only on Timer3. 2:  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 1x Gate Sync 01 ...

Page 130

... DS39881D-page 130 U-0 U-0 — — R/W-0 R/W-0 (1) TCKPS0 T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) /2) U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 (2) — TCS — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 131

... When 32-bit operation is enabled (T2CON<3> or T4CON<3> = 1), these bits have no effect on Timery Note 1: operation; all timer functions are set through T2CON and T4CON. If TCS = 1, RPINRx (TxCK) must be configured to an available RPn pin. See Section 10.4 “Peripheral 2: Pin Select” for more information.  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 (1) — ...

Page 132

... PIC24FJ64GA004 FAMILY NOTES: DS39881D-page 132  2010 Microchip Technology Inc. ...

Page 133

... An ‘x’ signal, register or bit name denotes the number of the capture channel. Note 1: This peripheral’s inputs must be assigned to an available RPn pin before use. Please see Section 10.4 2: “Peripheral Pin Select” for more information.  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Manual”, FIFO Edge Detection Logic ...

Page 134

... DS39881D-page 134 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 (1) ICOV ICBNE ICM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) U-0 U-0 — — bit 8 R/W-0 R/W-0 (1) (1) ICM1 ICM0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 135

... OCxIE bit. For further information on peripheral interrupts, refer to Section 7.0 “Interrupt Controller”.  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 10. To initiate another single pulse output, change the Timer and Compare register settings, if needed, and then issue a write to set the OCM bits to ‘ ...

Page 136

... Table 14-1 shows example PWM frequencies and resolutions for a device operating at 10 MIPS log 10 F • (Timer Prescale Value) PWM log ( /2, Doze mode and PLL are disabled. CY OSC CALCULATING THE PWM (1) PERIOD • (Timer Prescale Value Doze mode CY OSC (1) ) bits  2010 Microchip Technology Inc. ...

Page 137

... EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (F PWM Frequency 30.5 Hz Timer Prescaler Ratio 8 Period Register Value FFFFh Resolution (bits) 16 Based /2, Doze mode and PLL are disabled. Note 1: CY OSC  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY • (Timer 2 Prescale Value) /F )/log 2) bits PWM 10 2) bits 122 Hz 977 ...

Page 138

... This peripheral’s inputs and outputs must be assigned to an available RPn pin before use. Please see Section 10.4 4: “Peripheral Pin Select” section for more information. DS39881D-page 138 Set Flag bit (1) OCxIF Output S Q Logic R Output Enable 3 OCM2:OCM0 (4) Mode Select 0 1 Period match signals from time bases (see Note 3). (1) OCx (2) OCFA or OCFB  2010 Microchip Technology Inc. ...

Page 139

... RPORx (OCx) must be configured to an available RPn pin. For more information, see Section 10.4 Note 1: “Peripheral Pin Select”. OCFA pin controls OC1-OC4 channels. OCFB pin controls the OC5 channel. 2:  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — ...

Page 140

... PIC24FJ64GA004 FAMILY NOTES: DS39881D-page 140  2010 Microchip Technology Inc. ...

Page 141

... Enhanced Buffer mode. The module also supports a basic framed SPI protocol while operating in either Master or Slave mode. A total of four framed SPI configurations are supported.  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY The SPI serial interface consists of four pins: • SDIx: Serial Data Input • ...

Page 142

... Clear the SPIROV bit (SPIxSTAT<6>). 7. Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>). 1:1 to 1:8 Secondary Prescaler Select Edge Shift Control Transfer Write SPIxBUF 16 Internal Data Bus registers with MSTEN 1:1/4/16/64 Primary F CY Prescaler SPIxCON1<1:0> SPIxCON1<4:2> Enable Master Clock  2010 Microchip Technology Inc. ...

Page 143

... SDIx SPIxSR Transfer 8-Level FIFO Receive Buffer SPIxBUF Read SPIxBUF  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY To set up the SPI module for the Enhanced Buffer Slave mode of operation: 1. Clear the SPIxBUF register using interrupts: • Clear the SPIxIF bit in the respective IFSx register. • ...

Page 144

... Pin Select” for more information. DS39881D-page 144 U-0 U-0 — — SPIBEC2 R/W-0 R/W-0 SISEL2 SISEL1 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R-0 R-0 R-0 SPIBEC1 SPIBEC0 bit 8 R/W-0 R-0 R-0 SISEL0 SPITBF SPIRBF bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 145

... Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR. If SPIEN = 1, these functions must be assigned to available RPn pins before use. See Section 10.4 Note 1: “Peripheral Pin Select” for more information.  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY DS39881D-page 145 ...

Page 146

... R/W-0 R/W-0 R/W-0 (1) (2) DISSCK DISSDO MODE16 R/W-0 R/W-0 R/W-0 SPRE2 SPRE1 SPRE0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (3) (4) R/W-0 R/W-0 (3) SMP CKE bit 8 R/W-0 R/W-0 PPRE1 PPRE0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 147

... Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced Buffer enabled 0 = Enhanced Buffer disabled (Legacy mode)  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — ...

Page 148

... SDIx SDIx SDOx Serial Clock SCKx SCKx SSx (1) SSx SSEN (SPIxCON1<7> MSTEN (SPIxCON1<5> and SPIBEN (SPIxCON2<0> (2) (SPIxRXB) Shift Register (SPIxSR) LSb (2) (SPIxTXB) SPIx Buffer (2) (SPIxBUF) Shift Register (SPIxSR) MSb LSb 8-Level FIFO Buffer SPIx Buffer (2) (SPIxBUF)  2010 Microchip Technology Inc. ...

Page 149

... FIGURE 15-7: SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM PIC24F (SPI Slave, Frame Slave) FIGURE 15-8: SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM PIC24F (SPI Master, Frame Slave)  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY PROCESSOR 2 SDOx SDIx SDIx SDOx Serial Clock SCKx ...

Page 150

... Microchip Technology Inc. ...

Page 151

... ASCL1 and ASDA1 during device configuration. Pin assignment is controlled by the I2C1SEL Configu- ration bit; programming this bit (= 0) multiplexes the module to the ASCL1 and ASDA1 pins.  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 16.2 Communicating as a Master in a Single Master Environment ...

Page 152

... Bit Detect Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSB Reload Control Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read  2010 Microchip Technology Inc. ...

Page 153

... Note 1: Address will be Acknowledged only if GCEN = 1. 2: Match on this address can only occur on the upper byte in 10-Bit Addressing mode. 3:  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 16.4 Slave Address Masking The I2CxMSK register (Register 16-3) designates address bit positions as “don’t care” for both 7-Bit and 10-Bit Addressing modes ...

Page 154

... R/W-0, HC R/W-0, HC ACKEN RCEN PEN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2 C™ pins are controlled by port functions Slave slave slave) R/W-0 R/W-0 DISSLW SMEN bit 8 R/W-0, HC R/W-0, HC RSEN SEN bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 155

... Repeated Start condition not in progress bit 0 SEN: Start Condition Enabled bit (when operating Initiates Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence Start condition not in progress  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 2 C master. Applicable during master receive master ...

Page 156

... HS = Hardware Settable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2 C module is busy 2 C slave) R-0, HSC R-0, HSC GCSTAT ADD10 bit 8 R-0, HSC R-0, HSC RBF TBF bit 0 HSC = Hardware Settable, Clearable bit x = Bit is unknown  2010 Microchip Technology Inc. ...

Page 157

... Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 2 C slave device address byte. ...

Page 158

... DS39881D-page 158 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 AMSK4 AMSK3 AMSK2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 AMSK9 AMSK8 bit 8 R/W-0 R/W-0 AMSK1 AMSK0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 159

... This peripheral’s inputs and outputs must be assigned to an available RPn pin before use. Please Note: see Section 10.4 “Peripheral Pin Select” for more information.  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY • Fully Integrated Baud Rate Generator with 16-Bit Prescaler • ...

Page 160

... BRG timer to be reset (cleared). This ensures the BRG does not wait for a timer overflow before generating the new baud rate. /(16 * 65536). UART BAUD RATE WITH (1) BRGH = • (UxBRG + – • Baud Rate = F /2, Doze mode CY OSC /4 CY (1)  2010 Microchip Technology Inc. ...

Page 161

... Write ‘55h’ to UxTXREG – loads the Sync character into the transmit FIFO. 5. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits.  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 17.5 Receiving in 8-Bit or 9-Bit Data Mode 1. ...

Page 162

... U-0 (2) IREN RTSMD — R/W-0 R/W-0 R/W-0 RXINV BRGH PDSEL1 HC = Hardware Clearable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (3) (3) (3) R/W-0 R/W-0 UEN1 UEN0 bit 8 R/W-0 R/W-0 PDSEL0 STSEL bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 163

... If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Note 1: Section 10.4 “Peripheral Pin Select” for more information. This feature is only available for the 16x BRG mode (BRGH = 0). 2: Bit availability depends on pin availability. 3:  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY DS39881D-page 163 ...

Page 164

... U-0 R/W-0, HC R/W-0 — UTXBRK UTXEN R-1 R-0 R-0 RIDLE PERR FERR HC = Hardware Clearable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R-0 R-1 (1) UTXBF TRMT bit 8 R/C-0 R-0 OERR URXDA bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 165

... Receive buffer has data; at least one more character can be read 0 = Receive buffer is empty If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Note 1: Section 10.4 “Peripheral Pin Select” for more information.  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY DS39881D-page 165 ...

Page 166

... URX4 URX3 URX2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-x W-x — UTX8 bit 8 W-x W-x UTX1 UTX0 bit Bit is unknown U-0 R-0 — URX8 bit 8 R-0 R-0 URX1 URX0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 167

... PMP MODULE OVERVIEW PIC24F Parallel Master Port (1) PMA<10:2> are not available on 28-pin devices. Note 1:  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Key features of the PMP module include: • Programmable Address Lines • One Chip Select Line • Programmable Strobe Options: - Individual Read and Write Strobes or; ...

Page 168

... R/W-0 R/W-0 (1) (1) ADRMUX1 ADRMUX0 PTBEEN (2) (2) U-0 R/W-0 — CS1P U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (2) R/W-0 R/W-0 R/W-0 PTWREN PTRDEN bit 8 R/W-0 R/W-0 R/W-0 BEP WRSP RDSP bit Bit is unknown (1)  2010 Microchip Technology Inc. ...

Page 169

... Read strobe active-low (PMRD) For Master Mode 1 (PMMODE<9:8> Read/write strobe active-high (PMRD/PMWR Read/write strobe active-low (PMRD/PMWR) PMA<10:2> are not available on 28-pin devices. Note 1: These bits have no effect when their corresponding pins are used as address lines. 2:  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY DS39881D-page 169 ...

Page 170

... WAITM0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ; multiplexed address phase multiplexed address phase multiplexed address phase multiplexed address phase R/W-0 R/W-0 MODE1 MODE0 bit 8 R/W-0 R/W-0 (1) (1) WAITE1 WAITE0 bit Bit is unknown (1) ) (1)  2010 Microchip Technology Inc. ...

Page 171

... PTEN1:PTEN0: PMALH/PMALL Strobe Enable bits 1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL 0 = PMA1 and PMA0 pads functions as port I/O PMA<10:2> are not available on 28-pin devices. Note 1:  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 — — ...

Page 172

... Output buffer contains data that has not been transmitted DS39881D-page 172 U-0 R-0 R-0 — IB3F IB2F U-0 R-1 R-1 — OB3E OB2E U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared  2010 Microchip Technology Inc. R-0 R-0 IB1F IB0F bit 8 R-1 R-1 OB1E OB0E bit Bit is unknown ...

Page 173

... PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt Trigger input buffers To enable the actual RTCC output, the RTCOE (RCFGCAL) bit needs to be set. Note 1:  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — ...

Page 174

... PMRD PMDOUT2H (3) PMWR PMDOUT1<7:0> (0) PMDOUT2<7:0> (2) PMA<10:0> PMD<7:0> PMCS1 PMRD PMWR Address Bus Data Bus Control Lines Read Address Decode PMDIN1L (0) PMDIN1H (1) PMDIN2L (2) PMDIN2H (3) Input Register (Buffer) PMDIN1<7:0> (0) PMDIN1<15:8> (1) PMDIN2<7:0> (2) PMDIN2<15:8> (3) Address Bus Data Bus Control Lines  2010 Microchip Technology Inc. ...

Page 175

... PMD<7:0> PMALL PMALH PMCS1 PMRD PMWR FIGURE 18-8: EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION PIC24F PMD<7:0> PMALL PMA<10:8> PMCS1 PMRD PMWR  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY PMA<10:8> PMD<7:0> PMA<7:0> PMCS1 PMALL PMRD PMWR PMD<7:0> PMA<7:0> PMA<15:8> PMCS1 PMALL PMALH ...

Page 176

... Parallel EEPROM A<n:0> D<7:0> Parallel EEPROM A<n:1> D<7:0> LCD Controller D<7:0> RS R/W E Address Bus Data Bus Control Lines Address Bus Data Bus Control Lines Address Bus Data Bus Control Lines Address Bus Data Bus Control Lines  2010 Microchip Technology Inc. ...

Page 177

... RTCC Clock Domain 32.768 kHz Input from SOSC Oscillator RTCC Prescalers RTCC Timer Alarm Event Comparator Compare Registers with Masks Repeat Counter  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Manual”, CPU Clock Domain RCFGCAL ALCFGRPT 0.5s RTCVAL ALRMVAL RTCC Interrupt Logic YEAR ...

Page 178

... YEAR sequence and the setting of RTCWREN; therefore recommended that code bits follow the procedure in Example 19-1. ALRMVAL REGISTER MAPPING Alarm Value Register Window ALRMVAL<15:8> ALRMVAL<7:0> ALRMMIN ALRMSEC ALRMWD ALRMHR ALRMMNTH ALRMDAY — —  2010 Microchip Technology Inc. ...

Page 179

... The RCFGCAL register is only affected by a POR. Note 1: A write to the RTCEN bit is only allowed when RTCWREN = 1. 2: This bit is read-only cleared to ‘0’ write to the lower half of the MINSEC register. 3:  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R-0 R-0 R/W-0 (3) ...

Page 180

... Note 1: DS39881D-page 180 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1)  2010 Microchip Technology Inc. (1) U-0 U-0 — — bit 8 R/W-0 R/W-0 (1) RTSECSEL PMPTTL bit Bit is unknown ...

Page 181

... ARPT7:ARPT0: Alarm Repeat Counter Value bits 11111111 = Alarm will repeat 255 more times ... 00000000 = Alarm will not repeat The counter decrements on any alarm event. The counter is prevented from rolling over from 00h to FFh unless CHIME = 1.  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 AMASK2 ...

Page 182

... DAYTEN0 DAYONE3 DAYONE2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-x R/W-x YRONE1 YRONE0 bit Bit is unknown R-x R-x MTHONE1 MTHONE0 bit 8 R/W-x R/W-x DAYONE1 DAYONE0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 183

... Unimplemented: Read as ‘0’ bit 6-4 SECTEN2:SECTEN0: Binary Coded Decimal Value of Second’s Tens Digit; Contains a value from bit 3-0 SECONE3:SECONE0: Binary Coded Decimal Value of Second’s Ones Digit; Contains a value from  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 R/W-x — ...

Page 184

... HRTEN0 HRONE3 HRONE2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-x R/W-x MTHONE1 MTHONE0 bit 8 R/W-x R/W-x DAYONE1 DAYONE0 bit Bit is unknown (1) R/W-x R/W-x WDAY1 WDAY0 bit 8 R/W-x R/W-x HRONE1 HRONE0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 185

... Once the error is known, it must be converted to the number of error clock pulses per minute. EQUATION 19-1: (Ideal Frequency† – Measured Frequency Clocks per Minute † Ideal frequency = 32,768 Hz  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-x R/W-x R/W-x MINTEN0 MINONE3 MINONE2 ...

Page 186

... To avoid a false alarm event, the timer and alarm values should only be changed while the alarm is disabled (ALRMEN = 0 recommended that the ALCFGRPT register and CHIME bit be changed when RTCSYNC = 0. Day of the Week Month Day Hours Minutes Seconds  2010 Microchip Technology Inc. ...

Page 187

... X1 XOR 0 OUT IN D BIT 0 OUT 1 p_clk  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Consider the CRC equation: To program this polynomial into the CRC generator, the CRC register bits should be set as shown in Table 20-1. TABLE 20-1: Bit Name Manual”, PLEN3:PLEN0 X<15:1> ...

Page 188

... CSIDL bit must be cleared prior to entry into the mode. If CSIDL = 1, the module will behave the same way as it does in Sleep mode; pending interrupt events will be passed on, even though the module clocks are not available.  2010 Microchip Technology Inc BIT 15 p_clk ...

Page 189

... CRCGO: Start CRC bit 1 = Start CRC serial shifter 0 = CRC serial shifter turned off bit 3-0 PLEN3:PLEN0: Polynomial Length bits Denotes the length of the polynomial to be generated minus 1.  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R-0 R-0 R-0 VWORD4 VWORD3 VWORD2 ...

Page 190

... Unimplemented: Read as ‘0’ DS39881D-page 190 R/W-0 R/W-0 R/W-0 X12 X11 X10 R/W-0 R/W-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared n Enable bits R/W-0 R/W bit 8 R/W-0 U-0 X1 — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 191

... These voltage reference inputs may be shared with other analog input pins. The actual number of analog input pins and external voltage reference input configuration will depend on the specific device.  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY A block diagram of the A/D Converter is shown in Figure 21-1. ...

Page 192

... AD1CON2 AD1CON3 INH AD1CHS AD1PCFG AD1CSSL INL Sample Control Control Logic Input MUX Control Pin Config. Control ) is internally connected to analog channel AN15, which does not appear on any pin. BG Internal Data Bus 16 Comparator + R Conversion Logic Conversion Control  2010 Microchip Technology Inc. ...

Page 193

... SAMP: A/D Sample Enable bit 1 = A/D sample/hold amplifier is sampling input 0 = A/D sample/hold amplifier is holding bit 0 DONE: A/D Conversion Status bit 1 = A/D conversion is done 0 = A/D conversion is NOT done  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — — ...

Page 194

... Bit is cleared External V + pin REF External V + pin REF inputs are tied to V and V on 28-pin devices U-0 U-0 — — bit 8 R/W-0 R/W-0 BUFM ALTS bit Bit is unknown External V - pin REF External V - pin REF  2010 Microchip Technology Inc. ...

Page 195

... ADCS7:ADCS0: A/D Conversion Clock Select bits 11111111 ······ = Reserved 01000000 00111111 = 64 • ······ 00000001 = 2 • 00000000 = T CY  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 SAMC4 SAMC3 SAMC2 R/W-0 R/W-0 R/W-0 ...

Page 196

... CH0SB2 U-0 R/W-0 R/W-0 (1,2) (1,2) — CH0SA3 CH0SA2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared - R/W-0 R/W-0 (1,2) (1,2) CH0SB1 CH0SB0 bit 8 R/W-0 R/W-0 (1,2) (1,2) CH0SA1 CH0SA0 bit Bit is unknown (1,2) (1,2)  2010 Microchip Technology Inc. ...

Page 197

... CSSL12:CSSL0: A/D Input Pin Scan Selection bits 1 = Corresponding analog channel selected for input scan 0 = Analog channel omitted from input scan Analog channels AN6, AN7 and AN8 are unavailable on 28-pin devices; leave these corresponding bits Note 1: cleared.  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 PCFG12 ...

Page 198

... Threshold Voltage Leakage Current at the pin due to LEAKAGE various junctions R = Interconnect Resistance Sampling Switch Resistance Sample/Hold Capacitance (from DAC) HOLD PIN  5 k(Typical HOLD = DAC capacitance = 4.4 pF (Typical negligible if Rs  5 k.  2010 Microchip Technology Inc. ...

Page 199

... Voltage Level  2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY DS39881D-page 199 ...

Page 200

... PIC24FJ64GA004 FAMILY NOTES: DS39881D-page 200  2010 Microchip Technology Inc. ...

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