PIC24FJ16GA002-E/ML Microchip Technology, PIC24FJ16GA002-E/ML Datasheet - Page 214

• Manufacturer Part Number: PIC24FJ16GA002-E/ML
• Description: IC PIC MCU FLASH 16K 28-QFN
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ16GA002-E/ML

• Program Memory Type: FLASH
• Program Memory Size: 16KB (5.5K x 24)
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, MA240013, AC164127, DM300027, DV164033, DM240002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ64GA004 FAMILY
24.2.3
When
PIC24FJ64GA004 family devices also have a simple
brown-out capability. If the voltage supplied to the reg-
ulator is inadequate to maintain the tracking level, the
regulator Reset circuitry will generate a Brown-out
Reset. This event is captured by the BOR flag bit
(RCON<1>). The brown-out voltage levels are speci-
fied in Section 27.1 “DC Characteristics”.
24.2.4
The on-chip regulator is designed to meet the power-up
requirements for the device. If the application does not
use the regulator, then strict power-up conditions must
be adhered to. While powering up, V
never exceed V
24.2.5
When enabled, the on-chip regulator always consumes
a small incremental amount of current over I
including when the device is in Sleep mode, even
though the core digital logic does not require power. To
provide additional savings in applications where power
resources are critical, the regulator automatically
places itself into Standby mode whenever the device
goes into Sleep mode. This feature is controlled by the
VREGS bit (RCON<8>). By default, this bit is cleared,
which enables Standby mode.
For select PIC24FJ64GA004 family devices, the time
required for regulator wake-up from Standby mode is
controlled by the WUTSEL<1:0> Configuration bits
(CW2<14:13>). The default wake-up time for all
devices is 190 s. Where the WUTSEL Configuration
bits are implemented, a fast wake-up option is also
available. When WUTSEL<1:0> = 01, the regulator
wake-up time is 25 s.
When the regulator’s Standby mode is turned off
(VREGS = 1), Flash program memory stays powered
in Sleep mode and the device can wake-up in less than
10 s. When VREGS is set, the power consumption
while in Sleep mode will be approximately 40 A higher
than power consumption when the regulator is allowed
to enter Standby mode.
DS39881D-page 214
Note:
Note:
the
ON-CHIP REGULATOR AND BOR
POWER-UP REQUIREMENTS
For more information, see Section 27.0
“Electrical Characteristics”.
VOLTAGE REGULATOR STANDBY
MODE
This feature is implemented only on
PIC24FJ64GA004 family devices with a
major silicon revision level of B or later
(DEVREV register value is 3042h or
greater).
DD
on-chip
by 0.3 volts.
regulator
is
DDCORE
enabled,
DD
must
/I
PD
,
24.3
For PIC24FJ64GA004 family devices, the WDT is
driven by the LPRC oscillator. When the WDT is
enabled, the clock source is also enabled.
The nominal WDT clock source from LPRC is 31 kHz.
This feeds a prescaler that can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the FWPSA Configuration bit.
With a 31 kHz input, the prescaler yields a nominal
WDT time-out period (T
4 ms in 7-bit mode.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPS3:WDTPS0
Configuration bits (Flash Configuration Word 1<3:0>),
which allow the selection of a total of 16 settings, from
1:1 to 1:32,768. Using the prescaler and postscaler,
time-out periods ranging from 1 ms to 131 seconds can
be achieved.
The WDT, prescaler and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
• When a PWRSAV instruction is executed
• When the device exits Sleep or Idle mode to
• By a CLRWDT instruction during normal execution
If the WDT is enabled, it will continue to run during
Sleep or Idle modes. When the WDT time-out occurs,
the device will wake the device and code execution will
continue from where the PWRSAV instruction was exe-
cuted. The corresponding SLEEP or IDLE bits
(RCON<3:2>) will need to be cleared in software after
the device wakes up.
The WDT Flag bit, WDTO (RCON<4>), is not auto-
matically cleared following a WDT time-out. To detect
subsequent WDT events, the flag must be cleared in
software.
invoked by software (i.e., setting the OSWEN bit
after changing the NOSC bits), or by hardware
(i.e., Fail-Safe Clock Monitor)
(i.e., Sleep or Idle mode is entered)
resume normal operation
Note:
Watchdog Timer (WDT)
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
 2010 Microchip Technology Inc.
WDT
) of 1 ms in 5-bit mode, or