PIC24FJ16GA002-E/ML Microchip Technology, PIC24FJ16GA002-E/ML Datasheet - Page 107

• Manufacturer Part Number: PIC24FJ16GA002-E/ML
• Description: IC PIC MCU FLASH 16K 28-QFN
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ16GA002-E/ML

• Program Memory Type: FLASH
• Program Memory Size: 16KB (5.5K x 24)
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, MA240013, AC164127, DM300027, DV164033, DM240002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.4
A major challenge in general purpose devices is provid-
ing the largest possible set of peripheral features while
minimizing the conflict of features on I/O pins. The chal-
lenge is even greater on low pin count devices similar
to the PIC24FJ64GA family. In an application that
needs to use more than one peripheral multiplexed on
single pin, inconvenient workarounds in application
code or a complete redesign may be the only option.
The peripheral pin select feature provides an alterna-
tive to these choices by enabling the user’s peripheral
set selection and their placement on a wide range of
I/O pins. By increasing the pinout options available on
a particular device, users can better tailor the
microcontroller to their entire application, rather than
trimming the application to fit the device.
The peripheral pin select feature operates over a fixed
subset of digital I/O pins. Users may independently
map the input and/or output of any one of many digital
peripherals to any one of these I/O pins. Peripheral pin
select is performed in software and generally does not
require the device to be reprogrammed. Hardware
safeguards are included that prevent accidental or
spurious changes to the peripheral mapping once it has
been established.
10.4.1
The peripheral pin select feature is used with a range
of up to 26 pins; the number of available pins is depen-
dent on the particular device and its pincount. Pins that
support the peripheral pin select feature include the
designation “RPn” in their full pin designation, where
“RP” designates a remappable peripheral and “n” is the
remappable pin number. See Table 1-2 for pinout
options in Each Package Offering.
10.4.2
The peripherals managed by the peripheral pin select
are all digital only peripherals. These include general
serial communications (UART and SPI), general pur-
pose timer clock inputs, timer related peripherals (input
capture and output compare) and external interrupt
inputs. Also included are the outputs of the comparator
module, since these are discrete digital signals.
The peripheral pin select module is not applied to
I
or peripherals with analog inputs.
 2010 Microchip Technology Inc.
2
C™, change notification inputs, RTCC alarm outputs
Peripheral Pin Select
AVAILABLE PERIPHERALS
AVAILABLE PINS
PIC24FJ64GA004 FAMILY
A key difference between pin select and non pin select
peripherals is that pin select peripherals are not asso-
ciated with a default I/O pin. The peripheral must
always be assigned to a specific I/O pin before it can be
used. In contrast, non pin select peripherals are always
available on a default pin, assuming that the peripheral
is active and not conflicting with another peripheral.
10.4.2.1
When a pin selectable peripheral is active on a given
I/O pin, it takes priority over all other digital I/O and dig-
ital communication peripherals associated with the pin.
Priority is given regardless of the type of peripheral that
is mapped. Pin select peripherals never take priority
over any analog functions associated with the pin.
10.4.3
Peripheral pin select features are controlled through
two sets of Special Function Registers: one to map
peripheral inputs, and one to map outputs. Because
they are separately controlled, a particular peripheral’s
input and output (if the peripheral has both) can be
placed on any selectable function pin without
constraint.
The association of a peripheral to a peripheral select-
able pin is handled in two different ways, depending on
if an input or an output is being mapped.
10.4.3.1
The inputs of the peripheral pin select options are
mapped on the basis of the peripheral; that is, a control
register associated with a peripheral dictates the pin it
will be mapped to. The RPINRx registers are used to
configure peripheral input mapping (see Register 10-1
through Register 10-14). Each register contains two
sets of 5-bit fields, with each set associated with one of
the pin selectable peripherals. Programming a given
peripheral’s bit field with an appropriate 5-bit value
maps the RPn pin with that value to that peripheral. For
any given device, the valid range of values for any of
the bit fields corresponds to the maximum number of
peripheral pin selections supported by the device.
CONTROLLING PERIPHERAL PIN
SELECT
Peripheral Pin Select Function
Priority
Input Mapping
DS39881D-page 107