PIC24FJ16GA002-E/ML Microchip Technology, PIC24FJ16GA002-E/ML Datasheet - Page 106

• Manufacturer Part Number: PIC24FJ16GA002-E/ML
• Description: IC PIC MCU FLASH 16K 28-QFN
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ16GA002-E/ML

• Program Memory Type: FLASH
• Program Memory Size: 16KB (5.5K x 24)
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, MA240013, AC164127, DM300027, DV164033, DM240002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ64GA004 FAMILY
10.1.1
In addition to the PORT, LAT and TRIS registers for
data control, each port pin can also be individually con-
figured for either digital or open-drain output. This is
controlled by the Open-Drain Control register, ODCx,
associated with each port. Setting any of the bits con-
figures the corresponding pin to act as an open-drain
output.
The open-drain feature allows the generation of
outputs higher than V
digital only pins by using external pull-up resistors. The
maximum open-drain voltage allowed is the same as
the maximum V
10.2
The use of the AD1PCFG and TRIS registers control
the operation of the A/D port pins. The port pins that are
desired as analog inputs must have their correspond-
ing TRIS bit set (input). If the TRIS bit is cleared
(output), the digital output level (V
converted.
When reading the PORT register, all pins configured as
analog input channels will read as cleared (a low level).
Pins configured as digital inputs will not convert an
analog input. Analog levels on any pin that is defined as
a digital input (including the ANx pins) may cause the
input buffer to consume current that exceeds the
device specifications.
10.2.1
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically, this instruction
would be a NOP.
10.2.2
The voltage tolerance of pins used as device inputs is
dependent on the pin’s input function. Pins that are used
as digital only inputs are able to handle DC voltages up
to 5.5V, a level typical for digital logic circuits. In contrast,
pins that also have analog input functions of any kind
can only tolerate voltages up to V
beyond V
Table 10-1 summarizes the input capabilities. Refer to
Section 27.1 “DC Characteristics” for more details.
EXAMPLE 10-1:
DS39881D-page 106
MOV
MOV
NOP
BTSS
0xFF00, W0
W0, TRISBB
PORTB, #13
Configuring Analog Port Pins
DD
OPEN-DRAIN CONFIGURATION
I/O PORT WRITE/READ TIMING
ANALOG INPUT PINS AND
VOLTAGE CONSIDERATIONS
on these pins are always to be avoided.
IH
specification.
PORT WRITE/READ EXAMPLE
DD
(e.g., 5V) on any desired
DD
; Configure PORTB<15:8> as inputs
; and PORTB<7:0> as outputs
; Delay 1 cycle
; Next Instruction
. Voltage excursions
OH
or V
OL
) will be
TABLE 10-1:
10.3
The input change notification function of the I/O ports
allows the PIC24FJ64GA004 family of devices to gen-
erate interrupt requests to the processor in response to
a change of state on selected input pins. This feature is
capable of detecting input change of states even in
Sleep mode, when the clocks are disabled. Depending
on the device pin count, there are up to 22 external sig-
nals that may be selected (enabled) for generating an
interrupt request on a change of state.
There are four control registers associated with the CN
module. The CNEN1 and CNEN2 registers contain the
interrupt enable control bits for each of the CN input
pins. Setting any of these bits enables a CN interrupt
for the corresponding pins.
Each CN pin also has a weak pull-up connected to it.
The pull-ups act as a current source that is connected
to the pin, and eliminate the need for external resistors
when push button or keypad devices are connected.
The pull-ups are enabled separately using the CNPU1
and CNPU2 registers, which contain the control bits for
each of the CN pins. Setting any of the control bits
enables the weak pull-ups for the corresponding pins.
When the internal pull-up is selected, the pin pulls up to
V
pull-up source when the internal pull-ups are enabled,
as the voltage difference can cause a current path.
PORTA<4:0>
PORTB<15:12>
PORTB<4:0>
PORTC<2:0>
PORTA<10:7>
PORTB<11:5>
PORTC<9:3>
Note 1:
DD
Note:
Port or Pin
– 0.7V (typical). Make sure that there is no external
Input Change Notification
Unavailable on 28-pin devices.
Pull-ups on change notification pins
should always be disabled whenever the
port pin is configured as a digital output.
(1)
(1)
(1)
INPUT VOLTAGE LEVELS
Tolerated
Input
5.5V
V
 2010 Microchip Technology Inc.
DD
Only V
tolerated.
Tolerates input levels
above V
most standard logic.
Description
DD
DD
input levels
, useful for