PIC24FJ16GA002-E/ML Microchip Technology, PIC24FJ16GA002-E/ML Datasheet - Page 58

• Manufacturer Part Number: PIC24FJ16GA002-E/ML
• Description: IC PIC MCU FLASH 16K 28-QFN
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ16GA002-E/ML

• Program Memory Type: FLASH
• Program Memory Size: 16KB (5.5K x 24)
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, MA240013, AC164127, DM300027, DV164033, DM240002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ64GA004 FAMILY
TABLE 6-3:
DS39881D-page 58
POR
BOR
MCLR
WDT
Software
Illegal Opcode
Uninitialized W
Trap Conflict
Note 1:
Reset Type
2:
3:
4:
5:
6:
T
T
regulator is disabled.
T
T
oscillator clock to the system.
T
T
STARTUP
OST
POR
RST
LOCK
FSCM
= Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the
= Internal state Reset time.
= Power-on Reset delay (10 s nominal).
RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
EC, FRC, FRCDIV, LPRC T
ECPLL, FRCPLL
XT, HS, SOSC
XTPLL, HSPLL
EC, FRC, FRCDIV, LPRC
ECPLL, FRCPLL
XT, HS, SOSC
XTPLL, HSPLL
Any Clock
Any Clock
Any clock
Any Clock
Any Clock
Any Clock
= PLL lock time (2 ms nominal).
= Fail-Safe Clock Monitor delay.
= T
Clock Source
VREG
(10 s nominal) if on-chip regulator is enabled or T
T
T
T
POR
POR
POR
POR
T
T
T
T
SYSRST Delay
STARTUP
STARTUP
STARTUP
STARTUP
+ T
+ T
+ T
+ T
STARTUP
STARTUP
STARTUP
STARTUP
T
T
T
T
T
T
RST
RST
RST
RST
RST
RST
+ T
+ T
+ T
+ T
RST
RST
RST
RST
+ T
+ T
+ T
+ T
RST
RST
RST
RST
System Clock
T
T
OST
OST
T
T
Delay
T
T
LOCK
LOCK
+ T
+ T
OST
OST
—
—
—
—
—
—
—
—
LOCK
LOCK
PWRT
(64 ms nominal) if on-chip
 2010 Microchip Technology Inc.
FSCM
T
T
T
T
T
T
Delay
FSCM
FSCM
FSCM
FSCM
FSCM
FSCM
—
—
—
—
—
—
—
—
1, 2, 3
1, 2, 3, 5, 6
1, 2, 3, 4, 6
1, 2, 3, 4, 5, 6
2, 3
2, 3, 5, 6
2, 3, 4, 6
2, 3, 4, 5, 6
3
3
3
3
3
3
Notes