PIC24FJ16GA002-E/ML Microchip Technology, PIC24FJ16GA002-E/ML Datasheet - Page 213

• Manufacturer Part Number: PIC24FJ16GA002-E/ML
• Description: IC PIC MCU FLASH 16K 28-QFN
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ16GA002-E/ML

• Program Memory Type: FLASH
• Program Memory Size: 16KB (5.5K x 24)
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, MA240013, AC164127, DM300027, DV164033, DM240002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

24.2
All of the PIC24FJ64GA004 family of devices power
their core digital logic at a nominal 2.5V. This may
create an issue for designs that are required to operate
at a higher typical voltage, such as 3.3V. To simplify
system design, all devices in the PIC24FJ64GA004
family incorporate an on-chip regulator that allows the
device to run its core logic from V
The regulator is controlled by the DISVREG pin. Tying
V
vides power to the core from the other V
the regulator is enabled, a low-ESR capacitor (such as
ceramic) must be connected to the V
(Figure 24-1). This helps to maintain the stability of the
regulator. The recommended value for the filter capacitor
is provided in Section 27.1 “DC Characteristics”.
If DISVREG is tied to V
this case, separate power for the core logic at a nomi-
nal 2.5V must be supplied to the device on the
V
levels, typically 3.3V. Alternatively, the V
and V
nominal voltage. Refer to Figure 24-1 for possible
configurations.
24.2.1
When it is enabled, the on-chip regulator provides a
constant voltage of 2.5V nominal to the digital core
logic.
The regulator can provide this level from a V
2.5V, all the way up to the device’s V
have the capability to boost V
order to prevent “brown out” conditions when the volt-
age drops too low for the regulator, the regulator enters
Tracking mode. In Tracking mode, the regulator output
follows V
When the device enters Tracking mode, it is no longer
possible to operate at full speed. To provide information
about when the device enters Tracking mode, the
on-chip regulator includes a simple, Low-Voltage
Detect circuit. When V
ating voltage, the circuit sets the Low-Voltage Detect
Interrupt Flag, LVDIF (IFS4<8>). This can be used to
generate an interrupt and put the application into a
low-power operational mode, or trigger an orderly
shutdown.
Low-Voltage Detection is only available when the
regulator is enabled.
 2010 Microchip Technology Inc.
SS
DDCORE
to the pin enables the regulator, which in turn, pro-
DD
pins can be tied together to operate at a lower
On-Chip Voltage Regulator
DD
/V
CAP
, with a typical voltage drop of 100 mV.
VOLTAGE REGULATOR TRACKING
MODE AND LOW-VOLTAGE
DETECTION
pin to run the I/O pins at higher voltage
DD
DD
drops below full-speed oper-
, the regulator is disabled. In
DD
DD
levels below 2.5V. In
.
DDMAX
DDCORE
DD
DDCORE
. It does not
pins. When
DD
/V
of about
CAP
/V
PIC24FJ64GA004 FAMILY
CAP
pin
FIGURE 24-1:
24.2.2
When the voltage regulator is enabled, it takes approxi-
mately 20 s for it to generate output. During this time,
designated as T
T
operation after any power-down, including Sleep mode.
If the regulator is disabled, a separate Power-up Timer
(PWRT) is automatically enabled. The PWRT adds a
fixed delay of 64 ms nominal delay at device start-up.
STARTUP
Note 1:
Regulator Disabled (DISVREG tied to V
Regulator Disabled (V
Regulator Enabled (DISVREG tied to V
(10 F typ)
2.5V
2.5V
C
is applied every time the device resumes
EFC
ON-CHIP REGULATOR AND POR
(1)
(1)
These are typical operating voltages. Refer
to Section 27.1 “DC Characteristics” for
the full operating ranges of V
V
DDCORE
STARTUP
3.3V
3.3V
.
(1)
CONNECTIONS FOR THE
ON-CHIP REGULATOR
, code execution is disabled.
V
DISVREG
V
V
DD
DD
DDCORE
SS
V
DISVREG
V
V
V
DISVREG
V
V
PIC24FJ64GA
DD
DDCORE
SS
DD
DDCORE
SS
PIC24FJ64GA
PIC24FJ64GA
tied to V
/V
/V
/V
DS39881D-page 213
CAP
CAP
DDCORE
CAP
DD
and
SS
DD
):
):
):