PIC18F26J50-I/SS Microchip Technology, PIC18F26J50-I/SS Datasheet - Page 12
![IC PIC MCU FLASH 64K 2V 28-SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC18F26J50-I/SS
Manufacturer Part Number
PIC18F26J50-I/SS
Description
IC PIC MCU FLASH 64K 2V 28-SSOP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18LF24J50-ISS.pdf
(554 pages)
3.PIC18LF24J50-ISS.pdf
(12 pages)
Specifications of PIC18F26J50-I/SS
Core Size
8-Bit
Program Memory Size
64KB (32K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Controller Family/series
PIC18
No. Of I/o's
16
Ram Memory Size
3.6875KB
Cpu Speed
48MHz
No. Of Timers
2
Interface
EUSART, I2C, SPI, USB
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136, MA180024, DM183022
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Package
28SSOP
Device Core
PIC
Family Name
PIC18
Maximum Speed
48 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / Rohs Status
Details
PIC18F2XJXX/4XJXX FAMILY
3.2
Programming code memory is accomplished by first
loading data into the write buffer and then initiating a
programming sequence. The write buffer for all devices
in the PIC18F2XJXX/4XJXX family is 64 bytes. It can
be mapped to any 64-byte block beginning at 000000h.
The actual memory write sequence takes the contents
of this buffer and programs the 64-byte block of code
memory indicated by the Table Pointer.
Write buffer locations are not cleared following a write
operation; the buffer retains its data after the write is
complete. This means that the buffer must be written
with 64 bytes on each operation. If there are locations
in the code memory that are to remain empty, the
corresponding locations in the buffer must be filled with
FFFFh. This avoids rewriting old data from the previous
cycle.
TABLE 3-3:
DS39687E-page 12
Step 1: Enable writes.
Step 2: Load write buffer.
Step 3: Repeat for all but the last two bytes. Any unused locations should be filled with FFFFh.
Step 4: Load write buffer for last two bytes.
To continue writing data, repeat steps 2 through 4, where the Address Pointer is incremented by 2 at each iteration of the loop.
Command
0000
0000
0000
0000
0000
0000
0000
1101
1111
0000
4-Bit
Code Memory Programming
84 A6
0E <Addr[21:16]>
6E F8
0E <Addr[15:8]>
6E F7
0E <Addr[7:0]>
6E F6
<MSB><LSB>
<MSB><LSB>
00 00
WRITE CODE MEMORY CODE SEQUENCE
Data Payload
BSF
MOVLW <Addr[21:16]>
MOVWF TBLPTRU
MOVLW <Addr[15:8]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Write 2 bytes and post-increment address by 2.
Write 2 bytes and start programming.
NOP - hold PGC high for time P9.
EECON1, WREN
The programming duration is internally timed. After a
Start Programming command is issued (4-bit com-
mand, ‘1111’), a NOP is issued, where the 4th PGC is
held high for the duration of the programming time, P9.
The
PIC18F2XJXX/4XJXX family device is shown in
Table 3-3. The flowchart shown in Figure 3-5 depicts
the
PIC18F2XJXX/4XJXX family device. The timing
diagram that details the Start Programming command
and parameter P9 is shown in Figure 3-6.
Note 1: The TBLPTR register must point to the
logic
Core Instruction
code
same region when initiating the program-
ming sequence as it did when the write
buffers were loaded.
necessary
sequence
© 2009 Microchip Technology Inc.
to
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write
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