PIC18F26J50-I/SS Microchip Technology, PIC18F26J50-I/SS Datasheet - Page 20

• Manufacturer Part Number: PIC18F26J50-I/SS
• Description: IC PIC MCU FLASH 64K 2V 28-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26J50-I/SS

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC18
• No. Of I/o's: 16
• Ram Memory Size: 3.6875KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Interface: EUSART, I2C, SPI, USB
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3776 B
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136, MA180024, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Package: 28SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F2XJXX/4XJXX FAMILY
TABLE 5-4:
TABLE 5-5:
DS39687E-page 20
300000h CONFIG1L
300001h CONFIG1H
300002h CONFIG2L
300003h CONFIG2H
300004h CONFIG3L DSWDTPS3 DSWDTPS2 DSWDTPS1 DSWDTPS0 DSWDTEN DSBOREN
300005h CONFIG3H
300006h CONFIG4L
300007h CONFIG4H
3FFFFEh DEVID1
3FFFFFh DEVID2
Legend:
Note
DEBUG
XINST
STVREN
PLLDIV<2:0>
WDTEN
CP0
Note 1: The Configuration bits can only be programmed indirectly by programming the Flash Configuration Word.
(4)
File Name
Bit Name
1:
2:
3:
4:
2: The Configuration bits are reset to ‘1’ only on V
3: These bits are not implemented in PIC18F46J11 family devices.
4: Once this bit is cleared, all the Configuration registers which reside in the last page are also protected. To disable code
x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as ‘0’.
Values reflect the unprogrammed state as received from the factory and following Power-on Resets. In all other Reset states, the
configuration bytes maintain their previously programmed states.
The value of these bits in program memory should always be ‘1’. This ensures that the location is executed as a NOP if it is
accidentally executed.
These bits are not implemented in PIC18F46J11 family devices.
This bit should always be maintained at ‘0’.
protection, perform an ICSP™ Bulk Erase operation.
(3)
PIC18F46J11 AND PIC18F46J50 FAMILY DEVICES: CONFIGURATION BITS AND
DEVICE IDs
PIC18F46J11 AND PIC18F46J50 FAMILY DEVICES: BIT DESCRIPTIONS
WPCFG
DEBUG
DEV10
DEV2
IESO
Bit 7
—
—
—
—
Configuration
(2)
(2)
(2)
(2)
CONFIG1H
CONFIG1L
CONFIG1L
CONFIG1L
CONFIG1L
CONFIG1L
Words
WPEND
FCMEN
XINST
DEV1
DEV9
Bit 6
—
—
—
—
(2)
(2)
(2)
(2)
Background Debugger Enable bit
1 = Background debugger disabled, RB6 and RB7 configured as general purpose
0 = Background debugger enabled, RB6 and RB7 are dedicated to in-circuit debug
Enhanced Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode enabled
0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
Stack Overflow/Underflow Reset Enable bit
1 = Reset on stack overflow/underflow enabled
0 = Reset on stack overflow/underflow disabled
PLL Input Divider bits
Divider must be selected to provide a 4 MHz input into the 96 MHz PLL.
111 = No divide – oscillator used directly (4 MHz input)
110 = Oscillator divided by 2 (8 MHz input)
101 = Oscillator divided by 3 (12 MHz input)
100 = Oscillator divided by 4 (16 MHz input)
011 = Oscillator divided by 5 (20 MHz input)
010 = Oscillator divided by 6 (24 MHz input)
001 = Oscillator divided by 10 (40 MHz input)
000 = Oscillator divided by 12 (48 MHz input)
Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on SWDTEN bit)
Code Protection bit
1 = Program memory is not code-protected
0 = Program memory is code-protected
STVREN
WPFP5
DEV0
DEV8
I/O pins
Bit 5
—
—
—
—
—
(2)
(2)
(2)
(2)
LPT1OSC
WPFP4
REV4
DEV7
DD
Bit 4
—
—
—
—
—
(2)
(2)
(2)
(2)
Reset; it is reloaded with the programmed value at any device Reset.
PLLDIV2
MSSPMSK
WDTPS3
WPFP3
T1DIG
REV3
DEV6
Bit 3
—
—
(4)
(3)
PLLDIV1
Description
WDTPS2
WPFP2
FOSC2
REV2
DEV5
Bit 2
CP0
—
—
(3)
PLLDIV0
CPDIV1
WDTPS1
RTCOSC
WPFP1
FOSC1
REV1
DEV4
Bit 1
—
—
© 2009 Microchip Technology Inc.
(3)
(3)
DSWDTOSC
CPDIV0
IOL1WAY
WDTPS0
WDTEN
FOSC0
WPFP0
WPDIS
REV0
DEV3
Bit 0
(3)
Unprogrammed
11-1 1111
---- 1111
1111 1111
---- 1--1
1111 1111
---- ---1
xxxx xxxx
0100 00xx
111- 1111
---- 0111
Default/
Value
(1)