PIC18F26J50-I/SS Microchip Technology, PIC18F26J50-I/SS Datasheet - Page 18

• Manufacturer Part Number: PIC18F26J50-I/SS
• Description: IC PIC MCU FLASH 64K 2V 28-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26J50-I/SS

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC18
• No. Of I/o's: 16
• Ram Memory Size: 3.6875KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Interface: EUSART, I2C, SPI, USB
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3776 B
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136, MA180024, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Package: 28SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F2XJXX/4XJXX FAMILY
5.0
The Configuration Words of the PIC18F2XJXX/4XJXX
family devices are implemented as volatile memory
registers. All of the Configuration registers (CONFIG1L,
CONFIG1H,
CONFIG3H,
automatically loaded following each device Reset.
The data for these registers is taken from the four Flash
Configuration Words located at the end of program
memory. Configuration data is stored in order, starting
with CONFIG1L in the lowest Flash address and
ending with CONFIG4H in the highest. The mapping to
specific Configuration Words is shown in Table 5-1.
Users should always reserve these locations for
Configuration Word data and write their application
code accordingly.
The upper four bits of each Flash Configuration Word
should always be stored in program memory as ‘1111’.
This is done so these program memory addresses will
always be ‘1111 xxxx xxxx xxxx’ and interpreted
as a NOP instruction if they were ever to be executed.
Because the corresponding bits in the Configuration
registers are unimplemented, they will not change the
device’s configuration.
The Configuration and Device ID registers are
summarized in Table 5-2. A listing of the individual
Configuration bits and their options is provided in
Table 5-3.
TABLE 5-2:
DS39687E-page 18
300000h CONFIG1L
300001h CONFIG1H
300002h CONFIG2L
300003h CONFIG2H
300005h CONFIG3H
3FFFFEh DEVID1
3FFFFFh DEVID2
Legend:
Note 1:
File Name
2:
3:
CONFIGURATION WORD
- = unimplemented. Shaded cells are unimplemented, read as ‘0’.
The value of these bits in program memory should always be ‘1’. This ensures that the location is executed as a NOP if
it is accidentally executed.
This bit should always be maintained at ‘0’.
DEVID registers are read-only and cannot be programmed by the user.
CONFIG2L,
CONFIG4L
(3)
(3)
PIC18F45J10 FAMILY DEVICES: CONFIGURATION BITS AND DEVICE IDs
DEBUG
DEV10
DEV2
IESO
Bit 7
—
—
—
(1)
(1)
(1)
CONFIG2H,
and
FCMEN
XINST
DEV1
DEV9
Bit 6
—
—
—
CONFIG4H)
(1)
(1)
(1)
STVREN
CONFIG3L,
DEV0
DEV8
Bit 5
—
—
—
—
(1)
(1)
(1)
are
REV4
DEV7
Bit 4
—
—
—
—
—
(1)
(1)
(1)
WDTPS3
REV3
DEV6
TABLE 5-1:
Bit 3
—
CONFIG1L
CONFIG1H
CONFIG2L
CONFIG2H
CONFIG3L
CONFIG3H
CONFIG4L
CONFIG4H
Note 1:
—
—
—
Configuration
(2)
Register
2:
WDTPS2 WDTPS1 WDTPS0
FOSC2
REV2
DEV5
Bit 2
CP0
See Table 2-2 for the complete addresses
within code space for specific devices and
memory sizes.
Unimplemented in PIC18F45J10 family
devices.
—
—
(2)
(2)
MAPPING OF THE FLASH
CONFIGURATION WORDS TO
THE CONFIGURATION
REGISTERS
FOSC1
Configuration
REV1
DEV4
Bit 1
—
—
—
Byte
XFFBh
XFFCh
XFFDh
XFFEh
XFF8h
XFF9h
XFFAh
XFFFh
© 2009 Microchip Technology Inc.
Flash
(1)
CCP2MX
WDTEN
FOSC0
REV0
DEV3
Bit 0
—
Configuration
Unprogrammed
Register
Address
300000h
300001h
300002h
300003h
300004h
300005h
300006h
300007h
111- ---1
---- 01--
11-- -111
---- 1111
---- ---1
See Table
See Table
Default/
Value