DSPIC30F2011-20I/P Microchip Technology, DSPIC30F2011-20I/P Datasheet - Page 14
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DSPIC30F2011-20I/P
Manufacturer Part Number
DSPIC30F2011-20I/P
Description
IC DSPIC MCU/DSP 12K 18DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20ISO.pdf
(210 pages)
3.DSPIC30F2011-20ISO.pdf
(14 pages)
4.DSPIC30F2011-20ISO.pdf
(6 pages)
5.DSPIC30F2011-20ISO.pdf
(18 pages)
6.DSPIC30F2011-20IP.pdf
(26 pages)
7.DSPIC30F2011-20IP.pdf
(206 pages)
Specifications of DSPIC30F2011-20I/P
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-DIP (0.300", 7.62mm)
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
12
Flash Memory Size
12KB
Supply Voltage Range
2.5V To 5.5V
Package
18PDIP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
12
Interface Type
I2C/SPI/UART
On-chip Adc
8-chx12-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC30F005 - MODULE SCKT DSPIC30F 18DIP/SOICACICE0202 - ADAPTER MPLABICE 18P 300 MIL
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F2011-20IP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F2011-20I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
TABLE 5-7:
DS70102K-page 14
EBS
BSS<2:0>
BWRP
RSS<1:0>
ESS<1:0>
Bit Field
FBS
FBS
FBS
FSS
FSS
CONFIGURATION BITS DESCRIPTION (CONTINUED)
Register
Boot Segment Data EEPROM Code Protection (only present in dsPIC30F5011/
5013/6010A/6011A/6012A/6013A/6014A/6015)
1 = No Data EEPROM is reserved for Boot Segment
0 = 128 bytes of Data EEPROM are reserved for Boot Segment in dsPIC30F5011/
Boot Segment Program Memory Code Protection (only present in
dsPIC30F5011/5013/6010A/6011A/6012A/6013A/6014A/6015)
111 = No Boot Segment
110 = Standard security; Small-sized Boot Program Flash
101 = Standard security; Medium-sized Boot Program Flash
100 = Standard security; Large-sized Boot Program Flash
011 = No Boot Segment
010 = High security; Small-sized Boot Program Flash
001 = High security; Medium-sized Boot Program Flash
000 = High security; Large-sized Boot Program Flash
Boot Segment Program Memory Write Protection (only present in
dsPIC30F5011/5013/6010A/6011A/6012A/6013A/6014A/6015)
1 = Boot Segment program memory is not write-protected
0 = Boot Segment program memory is write-protected
Secure Segment Data RAM Code Protection (only present in dsPIC30F5011/
5013/6010A/6011A/6012A/6013A/6014A/6015)
11 = No Data RAM is reserved for Secure Segment
10 = Small-sized Secure RAM
01 = Medium-sized Secure RAM
00 = Large-sized Secure RAM
Secure Segment Data EEPROM Code Protection (only present in
dsPIC30F5011/5013/6010A/6011A/6012A/6013A/6014A/6015)
11 = No Data EEPROM is reserved for Secure Segment
10 = Small-sized Secure Data EEPROM
01 = Medium-sized Secure Data EEPROM
00 = Large-sized Secure Data EEPROM
5013, and 256 bytes in dsPIC30F6010A/6011A/6012A/6013A/6014A/6015
[(256 – N) bytes of RAM are reserved for Secure Segment]
[(768 – N) bytes of RAM are reserved for Secure Segment in dsPIC30F5011/
5013, and (2048 – N) bytes in dsPIC30F6010A/6011A/6012A/6013A/6014A/
6015]
[(1024 – N) bytes of RAM are reserved for Secure Segment in dsPIC30F5011/
5013, and (4096 – N) bytes in dsPIC30F6010A/6011A/6012A/6013A/6014A/
6015]
where N = Number of bytes of RAM reserved for Boot Sector.
[(128 – N) bytes of Data EEPROM are reserved for Secure Segment in
dsPIC30F5011/5013, and (256 – N) bytes in dsPIC30F6010A/6011A/6012A/
6013A/6014A/6015]
[(256 – N) bytes of Data EEPROM are reserved for Secure Segment in
dsPIC30F5011/5013, and (512 – N) bytes in dsPIC30F6010A/6011A/6012A/
6013A/6014A/6015]
[(512 – N) bytes of Data EEPROM are reserved for Secure Segment in
dsPIC30F5011/5013, (1024 – N) bytes in dsPIC30F6011A/6013A, and (2048 –
N) bytes in dsPIC30F6010A/6012A/6014A/6015]
where N = Number of bytes of Data EEPROM reserved for Boot Sector.
[Boot Segment starts after BS and ends at 0x0003FF]
[Boot Segment starts after BS and ends at 0x000FFF]
[Boot Segment starts after BS and ends at 0x001FF]
[Boot Segment starts after BS and ends at 0x0003FF]
[Boot Segment starts after BS and ends at 0x000FFF]
[Boot Segment starts after BS and ends at 0x001FFF]
Description
© 2010 Microchip Technology Inc.