PIC18F86J90-I/PT Microchip Technology, PIC18F86J90-I/PT Datasheet - Page 177

• Manufacturer Part Number: PIC18F86J90-I/PT
• Description: IC PIC MCU FLASH 64KB 80-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J90-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 67
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3923 B
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 67
• Number Of Timers: 4
• Operating Supply Voltage: 2.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16.3
In Compare mode, the 16-bit CCPR2 register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCP2
pin can be:
• driven high
• driven low
• toggled (high-to-low or low-to-high)
• remain unchanged (that is, reflects the state of the
The action on the pin is based on the value of the mode
select bits (CCP2M<3:0>). At the same time, the
interrupt flag bit, CCP2IF, is set.
16.3.1
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
16.3.2
Timer1 and/or Timer3 must be running in Timer mode,
or Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
FIGURE 16-3:
 2010 Microchip Technology Inc.
I/O latch)
Note:
Compare Mode
CCP PIN CONFIGURATION
Clearing the CCP2CON register will force
the RC1 or RE7 compare output latch
(depending on device configuration) to the
default low level. This is not the PORTC or
PORTE I/O data latch.
TIMER1/TIMER3 MODE SELECTION
0
1
COMPARE MODE OPERATION BLOCK DIAGRAM
CCPR2H
CCPR1H
TMR1H
TMR3H
T3CCP1
Comparator
Comparator
CCPR2L
CCPR1L
TMR1L
TMR3L
Compare
Compare
Match
Match
0
1
Set CCP1IF
T3CCP2
Set CCP2IF
(Timer1/Timer3 Reset, A/D Trigger)
PIC18F87J90 FAMILY
16.3.3
When the Generate Software Interrupt mode is chosen
(CCP2M<3:0> = 1010), the CCP2 pin is not affected.
Only a CCP interrupt is generated, if enabled, and the
CCP2IE bit is set.
16.3.4
Both CCP modules are equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the
(CCP2M<3:0> = 1011).
For either CCP module, the Special Event Trigger resets
the Timer register pair for whichever timer resource is
currently assigned as the module’s time base. This
allows the CCPRx registers to serve as a programmable
period register for either timer.
The Special Event Trigger for CCP2 can also start an
A/D conversion. In order to do this, the A/D Converter
must already be enabled.
Special Event Trigger
Special Event Trigger
Note:
CCP1CON<3:0>
(Timer1 Reset)
CCP2CON<3:0>
Output
Compare
Output
Logic
4
Logic
4
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
The Special Event Trigger of CCP1 only
resets Timer1/Timer3 and cannot start an
A/D conversion, even when the A/D
Converter is enabled.
Special
S
R
S
R
Q
Q
Output Enable
Output Enable
Event
TRIS
TRIS
DS39933D-page 177
CCP1 Pin
CCP2 Pin
Trigger
mode