PIC18F86J90-I/PT Microchip Technology, PIC18F86J90-I/PT Datasheet - Page 206

• Manufacturer Part Number: PIC18F86J90-I/PT
• Description: IC PIC MCU FLASH 64KB 80-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J90-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 67
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3923 B
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 67
• Number Of Timers: 4
• Operating Supply Voltage: 2.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87J90 FAMILY
17.9
The LCD timing generation provides an interrupt that
defines the LCD frame timing. This interrupt can be
used to coordinate the writing of the pixel data with the
start of a new frame. Writing pixel data at the frame
boundary allows a visually crisp transition of the image.
This interrupt can also be used to synchronize external
events to the LCD. For example, the interface to an
external segment driver can be synchronized for a
segment data update to the LCD frame.
A new frame is defined to begin at the leading edge of
the COM0 common signal. The interrupt will be set
immediately after the LCD controller completes
accessing all pixel data required for a frame. This will
occur at a fixed interval before the frame boundary
(T
will begin to access data for the next frame within the
interval from the interrupt to when the controller begins
to access data after the interrupt (T
must be written within T
controller will begin to access the data for the next
frame.
FIGURE 17-17:
DS39933D-page 206
FINT
T
T
), as shown in Figure 17-17. The LCD controller
COM0
COM1
COM2
COM3
FWR
FINT
LCD Interrupts
= T
= (T
(T
FRAME
FWR
FWR
/2 – (2 T
/2 – (1 T
Boundary
/2 * (LMUX<1:0> + 1) + T
Frame
EXAMPLE WAVEFORMS AND INTERRUPT TIMING
IN QUARTER DUTY CYCLE DRIVE
FWR
CY
CY
, as this is when the LCD
+ 40 ns)) Minimum = 1.5(T
+ 40 ns)) Maximum = 1.5(T
FWR
). New data
CY
/2
2 Frames
FRAME
FRAME
Boundary
Frame
/4) – (2 T
/4) – (1 T
When the LCD driver is running with Type-B wave-
forms, and the LMUX<1:0> bits are not equal to ‘00’,
there are some additional issues that must be
addressed. Since the DC voltage on the pixel takes two
frames to maintain zero volts, the pixel data must not
change between subsequent frames. If the pixel data
was allowed to change, the waveform for the odd
frames would not necessarily be the complement of the
waveform generated in the even frames and a DC
component would be introduced into the panel. There-
fore, when using Type-B waveforms, the user must
synchronize the LCD pixel updates to occur within a
subframe after the frame interrupt.
To correctly sequence writing while in Type-B, the
interrupt will only occur on complete phase intervals. If
the user attempts to write when the write is disabled,
the WERR (LCDCON<5>) bit is set.
Note:
CY
CY
LCD
Interrupt
Occurs
+ 40 ns)
+ 40 ns)
The interrupt is not generated when the
Type-A waveform is selected and when the
Type-B with no multiplex (static) is
selected.
T
FWR
T
FINT
 2010 Microchip Technology Inc.
Controller Accesses
Next Frame Data
Boundary
Frame
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0