ATMEGA328P-AU Atmel, ATMEGA328P-AU Datasheet - Page 303

MCU AVR 32K FLASH 32TQFP

ATMEGA328P-AU

Manufacturer Part Number
ATMEGA328P-AU
Description
MCU AVR 32K FLASH 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar

Specifications of ATMEGA328P-AU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
20MHz
Total Internal Ram Size
2KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
2.5/3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
1.8V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Package Type
TQFP
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA328P-20AU
ATMEGA328P-20AU
Q3790246

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28.6
28.6.1
8271D–AVR–05/11
Parallel Programming Parameters, Pin Mapping, and Commands
Signal Names
Table 28-12. No. of Words in a Page and No. of Pages in the EEPROM
This section describes how to parallel program and verify Flash Program memory, EEPROM
Data memory, Memory Lock bits, and Fuse bits in the ATmega48A/PA/88A/PA/168A/PA/328/P.
Pulses are assumed to be at least 250 ns unless otherwise noted.
In this section, some pins of the ATmega48A/PA/88A/PA/168A/PA/328/P are referenced by sig-
nal names describing their functionality during parallel programming, see
28-13. Pins not described in the following table are referenced by pin names.
The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse.
The bit coding is shown in
When pulsing WR or OE, the command loaded determines the action executed. The different
Commands are shown in
Figure 28-1. Parallel Programming
Note:
Device
ATmega168A
ATmega168PA
ATmega328
ATmega328P
V
CC
- 0.3V < AV
ATmega48A/PA/88A/PA/168A/PA/328/P
EEPROM
512bytes
512bytes
1Kbytes
1Kbytes
CC
Size
< V
Table
Table
RDY/BSY
CC
PAGEL
+12 V
BS1
XA0
XA1
BS2
WR
+ 0.3V, however, AV
OE
28-16.
28-15.
4bytes
4bytes
4bytes
4bytes
Page
Size
PD1
PD2
PD3
PD4
PD5
PD6
RESET
XTAL1
GND
PD7
PC2
PC[1:0]:PB[5:0]
PCWORD
EEA[1:0]
EEA[1:0]
EEA[1:0]
EEA[1:0]
CC
should always be within 4.5 - 5.5V
AVCC
VCC
+4.5 - 5.5V
+4.5 - 5.5V
Pages
No. of
128
128
256
256
DATA
PCPAGE
EEA[8:2]
EEA[8:2]
EEA[9:2]
EEA[9:2]
Figure 28-1
EEAMSB
and
8
8
9
9
Table
303

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