PIC16F737-I/SP Microchip Technology, PIC16F737-I/SP Datasheet - Page 172

• Manufacturer Part Number: PIC16F737-I/SP
• Description: IC PIC MCU FLASH 4KX14 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F737-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: AUSART/CCP/I2C/MSSP/SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 3
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3DBF777 - BOARD DAUGHTER ICEPIC3
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PICmicro MID-RANGE MCU FAMILY
11.3
DS31011A-page 11-4
Instruction
PC
(Program
Counter)
Fetch
Instruction
Execute
TMR0
PC
(Program
Counter)
Instruction
Fetch
TMR0
Instruction
Executed
Operation
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
T0
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
T0
PC-1
PC-1
Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the Timer0 mod-
ule will increment every instruction cycle (without prescaler). If the TMR0 register is written, the
increment is inhibited for the following two instruction cycles
user can work around this by writing an adjusted value to the TMR0 register.
Counter mode is selected by setting the T0CS bit (OPTION<5>). In counter mode, Timer0 will
increment either on every rising or falling edge of the T0CKI pin. The incrementing edge is deter-
mined by the Timer0 Source Edge Select the T0SE bit (OPTION<4>). Clearing the T0SE bit
selects the rising edge. Restrictions on the external clock input are discussed in detail in Subsec-
tion
The prescaler is mutually exclusively shared between the Timer0 module and the Watchdog
Timer. The prescaler assignment is controlled in software by the PSA control bit (OPTION<3>).
Clearing the PSA bit will assign the prescaler to the Timer0 module. The prescaler is not readable
or writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4,...,
1:256 are selectable. Subsection
Any write to the TMR0 register will cause a 2 instruction cycle (2T
TMR0 register has been written with the new value, TMR0 will not be incremented until the third
instruction cycle later
write to the TMR0 register will immediately update the TMR0 register and clear the prescaler. The
incrementing of Timer0 (TMR0 and Prescaler) will also be inhibited 2 instruction cycles (T
if the prescaler is configured as 2, then after a write to the TMR0 register TMR0 will not increment
for 4 Timer0 clocks
clocks later.
Figure 11-2: Timer0 Timing: Internal Clock/No Prescale
Figure 11-3: Timer0 Timing: Internal Clock/Prescale 1:2
MOVWF TMR0
11.5 “Using Timer0 with an External Clock”
MOVWF TMR0
T0+1
PC
T0+1
PC
MOVF TMR0,W
Write TMR0
executed
MOVF TMR0,W
T0+2
Write TMR0
executed
PC+1
(Figure
PC+1
(Figure
MOVF TMR0,W
11-3). After that, TMR0 will increment every prescaler number of
Read TMR0
reads NT0
11-2). When the prescaler is assigned to the Timer0 module, any
MOVF TMR0,W
NT0
Read TMR0
reads NT0
PC+2
11.6 “TMR0 Prescaler”
PC+2
MOVF TMR0,W
Read TMR0
reads NT0
MOVF TMR0,W
Read TMR0
reads NT0
NT0
PC+3
PC+3
NT0
.
MOVF TMR0,W
Read TMR0
reads NT0
MOVF TMR0,W
Read TMR0
reads NT0
NT0
PC+4
PC+4
details the operation of the prescaler.
(Figure 11-2
MOVF TMR0,W
Read TMR0
reads NT0
MOVF TMR0,W
1997 Microchip Technology Inc.
CY
Read TMR0
reads NT0 + 1
NT0+1
PC+5
) inhibit. That is, after the
PC+5
and
Figure
Read TMR0
reads NT0 + 1
NT0+1
Read TMR0
reads NT0 + 2
NT0+2
PC+6
PC+6
11-3). The
CY
). So
T0