PIC18F2510-I/SP Microchip Technology, PIC18F2510-I/SP Datasheet - Page 154
![IC MCU FLASH 16KX16 28-DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18F2510-I/SP
Manufacturer Part Number
PIC18F2510-I/SP
Description
IC MCU FLASH 16KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18LF2410-ISO.pdf
(376 pages)
4.PIC18LF2410-ISO.pdf
(8 pages)
5.PIC18LF2410-ISO.pdf
(16 pages)
6.PIC18LF2410-ISO.pdf
(6 pages)
7.PIC18LF2410-ISO.pdf
(6 pages)
8.PIC18LF2410-ISO.pdf
(8 pages)
9.PIC18F2510-ISP.pdf
(378 pages)
Specifications of PIC18F2510-I/SP
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
25
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
25
Ram Memory Size
1.5KB
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F2510-I/SP
Manufacturer:
TM
Quantity:
50 000
- PIC16F616T-ISL PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18LF2410-ISO PDF datasheet #3
- PIC18LF2410-ISO PDF datasheet #4
- PIC18LF2410-ISO PDF datasheet #5
- PIC18LF2410-ISO PDF datasheet #6
- PIC18LF2410-ISO PDF datasheet #7
- PIC18LF2410-ISO PDF datasheet #8
- PIC18F2510-ISP PDF datasheet #9
- Current page: 154 of 378
- Download datasheet (7Mb)
PIC18F2X1X/4X1X
16.3.1
The MSSP module has four registers for SPI mode
operation. These are:
• MSSP Control Register 1 (SSPCON1)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
• MSSP Shift Register (SSPSR) – Not directly
SSPCON1 and SSPSTAT are the control and status
registers in SPI mode operation. The SSPCON1
register is readable and writable. The lower 6 bits of
the SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
REGISTER 16-1:
DS39636C-page 152
(SSPBUF)
accessible
REGISTERS
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SSPSTAT: MSSP STATUS REGISTER (SPI MODE)
bit 7
SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI operation is used in Slave mode.
CKE: SPI Clock Select bit
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
D/A: Data/Address bit
Used in I
P: Stop bit
Used in I
cleared.
S: Start bit
Used in I
R/W: Read/Write bit Information
Used in I
UA: Update Address bit
Used in I
BF: Buffer Full Status bit (Receive mode only)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Legend:
R = Readable bit
-n = Value at POR
R/W-0
Note:
SMP
2
2
2
2
2
C mode only.
C mode only. This bit is cleared when the MSSP module is disabled; SSPEN is
C mode only.
C mode only.
C mode only.
Polarity of clock state is set by the CKP bit (SSPCON1<4>).
R/W-0
CKE
W = Writable bit
‘1’ = Bit is set
D/A
Preliminary
R-0
R-0
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not double-
buffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.
P
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R-0
S
R/W
R-0
© 2007 Microchip Technology Inc.
x = Bit is unknown
R-0
UA
R-0
BF
bit 0
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