PIC18F8410-I/PT Microchip Technology, PIC18F8410-I/PT Datasheet - Page 215
PIC18F8410-I/PT
Manufacturer Part Number
PIC18F8410-I/PT
Description
IC PIC MCU FLASH 8KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F6310-IPT.pdf
(412 pages)
2.PIC18F6310-IPT.pdf
(16 pages)
3.PIC18F6310-IPT.pdf
(4 pages)
4.PIC18F6310-IPT.pdf
(28 pages)
5.PIC18F6310-IPT.pdf
(6 pages)
6.PIC18F6310-IPT.pdf
(4 pages)
7.PIC18F8410-IPT.pdf
(404 pages)
Specifications of PIC18F8410-I/PT
Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
70
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Controller Family/series
PIC18
No. Of I/o's
70
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
5
Interface
I2C, SPI, USART
Embedded Interface Type
I2C, SPI, USART
Rohs Compliant
Yes
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SPI, I2C, EUSART, AUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163032
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F8410-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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17.1
The BRG is a dedicated, 8-bit or 16-bit generator that
supports both the Asynchronous and Synchronous
modes of the EUSART. By default, the BRG operates
in 8-bit mode; setting the BRG16 bit (BAUDCON1<3>)
selects 16-bit mode.
The SPBRGH1:SPBRG1 register pair controls the
period of a free running timer. In Asynchronous mode,
bits BRGH (TXSTA1<2>) and BRG16 (BAUDCON1<3>)
also control the baud rate. In Synchronous mode, BRGH
is ignored. Table 17-1 shows the formula for computa-
tion of the baud rate for different EUSART modes that
only apply in Master mode (internally generated clock).
Given the desired baud rate and F
integer value for the SPBRGH1:SPBRG1 registers can
be calculated using the formulas in Table 17-1. From
this, the error in baud rate can be determined. An
example calculation is shown in Example 17-1. Typical
baud
Asynchronous modes are shown in Table 17-2. It may
TABLE 17-1:
EXAMPLE 17-1:
TABLE 17-2:
© 2007 Microchip Technology Inc.
Legend: x = Don’t care, n = Value of SPBRGH1:SPBRG1 register pair
TXSTA1
RCSTA1
BAUDCON1
SPBRGH1
SPBRG1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
For a device with F
Desired Baud Rate
Solving for SPBRGH1:SPBRG1:
Calculated Baud Rate = 16000000/(64 (25 + 1))
Error
SYNC
Name
0
0
0
0
1
1
rates
EUSART Baud Rate Generator
(BRG)
Configuration Bits
and
EUSART1 Baud Rate Generator Register High Byte
EUSART1 Baud Rate Generator Register Low Byte
ABDOVF
CSRC
SPEN
Bit 7
BAUD RATE FORMULAS
BRG16
REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
OSC
X = ((F
error
0
0
1
1
0
1
CALCULATING BAUD RATE ERROR
= F
= ((16000000/9600)/64) – 1
= [25.042] = 25
= 9615
= (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
= (9615 – 9600)/9600 = 0.16%
of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
RCIDL
values
OSC
Bit 6
RX9
TX9
OSC
/(64 ([SPBRGH1:SPBRG1] + 1))
BRGH
/Desired Baud Rate)/64) – 1
0
1
0
1
x
x
for
OSC
TXEN
SREN
Bit 5
—
, the nearest
the
PIC18F6310/6410/8310/8410
various
CREN
SYNC
SCKP
Bit 4
Preliminary
BRG/EUSART Mode
16-bit/Asynchronous
16-bit/Asynchronous
8-bit/Asynchronous
8-bit/Asynchronous
16-bit/Synchronous
8-bit/Synchronous
SENDB
ADDEN
BRG16
Bit 3
be advantageous to use the high baud rate (BRGH = 1)
or the 16-bit BRG to reduce the baud rate error, or
achieve a slow baud rate for a fast oscillator frequency.
Writing a new value to the SPBRGH1:SPBRG1
registers causes the BRG timer to be reset (or cleared).
This ensures the BRG does not wait for a timer
overflow before outputting the new baud rate.
17.1.1
The device clock is used to generate the desired baud
rate. When one of the power-managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRG1 register pair.
17.1.2
The data on the RX1 pin is sampled three times by a
majority detect circuit to determine if a high or a low
level is present at the RX1 pin.
BRGH
FERR
Bit 2
—
OPERATION IN POWER-MANAGED
MODES
SAMPLING
OERR
TRMT
WUE
Bit 1
Baud Rate Formula
F
F
ABDEN
F
RX9D
OSC
OSC
TX9D
Bit 0
OSC
/[64 (n + 1)]
/[16 (n + 1)]
/[4 (n + 1)]
DS39635B-page 213
Reset Values
on Page
59
59
60
60
59
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