PIC18F8410-I/PT Microchip Technology, PIC18F8410-I/PT Datasheet - Page 236
PIC18F8410-I/PT
Manufacturer Part Number
PIC18F8410-I/PT
Description
IC PIC MCU FLASH 8KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F6310-IPT.pdf
(412 pages)
2.PIC18F6310-IPT.pdf
(16 pages)
3.PIC18F6310-IPT.pdf
(4 pages)
4.PIC18F6310-IPT.pdf
(28 pages)
5.PIC18F6310-IPT.pdf
(6 pages)
6.PIC18F6310-IPT.pdf
(4 pages)
7.PIC18F8410-IPT.pdf
(404 pages)
Specifications of PIC18F8410-I/PT
Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
70
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Controller Family/series
PIC18
No. Of I/o's
70
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
5
Interface
I2C, SPI, USART
Embedded Interface Type
I2C, SPI, USART
Rohs Compliant
Yes
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SPI, I2C, EUSART, AUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163032
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F8410-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC18F6310/6410/8310/8410
18.1
The BRG is a dedicated 8-bit generator that supports
both the Asynchronous and Synchronous modes of the
AUSART.
The SPBRG2 register controls the period of a free
running timer. In Asynchronous mode, bit BRGH
(TXSTA<2>) also controls the baud rate. In Synchro-
nous mode, BRGH is ignored. Table 18-1 shows the
formula for computation of the baud rate for different
AUSART modes, which only apply in Master mode
(internally generated clock).
Given the desired baud rate and F
integer value for the SPBRG2 register can be calcu-
lated using the formulas in Table 18-1. From this, the
error in baud rate can be determined. An example
calculation is shown in Example 18-1. Typical baud
rates and error values for the various Asynchronous
modes are shown in Table 18-2. It may be advanta-
geous to use the high baud rate (BRGH = 1) to reduce
the baud rate error, or achieve a slow baud rate for a
fast oscillator frequency.
TABLE 18-1:
EXAMPLE 18-1:
TABLE 18-2:
DS39635B-page 234
Legend: x = Don’t care, n = Value of SPBRG2 register
TXSTA2
RCSTA2
SPBRG2
Legend: Shaded cells are not used by the BRG.
For a device with F
Desired Baud Rate
Solving for SPBRG2:
Calculated Baud Rate = 16000000/(64 (25 + 1))
Error
Name
SYNC
Configuration Bits
0
0
1
AUSART Baud Rate Generator
(BRG)
AUSART2 Baud Rate Generator Register
CSRC
SPEN
Bit 7
BAUD RATE FORMULAS
REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
X = ((F
OSC
BRGH
CALCULATING BAUD RATE ERROR
= F
= ((16000000/9600)/64) – 1
= [25.042] = 25
= 9615
= (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
= (9615 – 9600)/9600 = 0.16%
of 16 MHz, desired baud rate of 9600, Asynchronous mode, BRGH = 0:
0
1
x
OSC
Bit 6
OSC
RX9
TX9
/(64 ([SPBRG2] + 1))
/Desired Baud Rate)/64) – 1
OSC
TXEN
SREN
Bit 5
, the nearest
BRG/AUSART Mode
Asynchronous
Asynchronous
Synchronous
Preliminary
SYNC
CREN
Bit 4
ADDEN
Writing a new value to the SPBRG2 register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before outputting
the new baud rate.
18.1.1
The device clock is used to generate the desired baud
rate. When one of the power-managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRG2 register.
18.1.2
The data on the RX2 pin is sampled three times by a
majority detect circuit to determine if a high or a low
level is present at the RX2 pin.
Bit 3
—
BRGH
FERR
Bit 2
OPERATION IN POWER-MANAGED
MODES
SAMPLING
OERR
TRMT
Baud Rate Formula
Bit 1
© 2007 Microchip Technology Inc.
F
F
F
OSC
OSC
OSC
/[64 (n + 1)]
/[16 (n + 1)]
/[4 (n + 1)]
TX9D
RX9D
Bit 0
Values on
Reset
Page
60
60
60
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