AT91SAM7S32B-MU Atmel, AT91SAM7S32B-MU Datasheet
AT91SAM7S32B-MU
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AT91SAM7S32B-MU Summary of contents
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Features ® • Incorporates the ARM7TDMI ARM – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt ™ – EmbeddedICE In-circuit Emulation, Debug Communication Channel Support • Internal High-speed Flash – 512 Kbytes (AT91SAM7S512) Organized in ...
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... One Two-wire Interface (TWI) – Master Mode Support Only, All Two-wire Atmel EEPROMs and I (AT91SAM7S512/256/128/64/321/32) – Master, Multi-Master and Slave Mode Support, All Two-wire Atmel EEPROMs and I (AT91SAM7S161/16) • One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os ™ ...
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... Description Atmel’s AT91SAM7S is a series of low pincount Flash microcontrollers based on the 32-bit ARM RISC processor. It features a high-speed Flash and an SRAM, a large set of peripherals, includ- ing a USB 2.0 device (except for the AT91SAM7S32 and AT91SAM7S16), and a complete set of system functions minimizing the number of external components. The device is an ideal migration path for 8-bit microcontroller users looking for additional performance and extended memory ...
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Block Diagram Figure 2-1. AT91SAM7S512/256/128/64/321/161 Block Diagram TDI TDO JTAG TMS SCAN TCK JTAGSEL System Controller TST FIQ IRQ0-IRQ1 PCK0-PCK2 PLLRC PLL XIN OSC XOUT RCOSC VDDCORE BOD POR VDDCORE NRST DRXD DTXD RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 ...
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Figure 2-2. AT91SAM7S32/16 Block Diagram TDI TDO TMS TCK JTAGSEL System Controller TST FIQ IRQ0 PCK0-PCK2 PLLRC PLL XIN OSC XOUT VDDCORE BOD POR VDDCORE NRST DRXD DTXD RXD0 TXD0 SCK0 RTS0 CTS0 NPCS0 NPCS1 NPCS2 NPCS3 MISO MOSI SPCK ...
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Signal Description Table 3-1. Signal Description List Signal Name Function Voltage and ADC Regulator Power Supply VDDIN Input VDDOUT Voltage Regulator Output VDDFLASH Flash Power Supply VDDIO I/O Lines Power Supply VDDCORE Core Power Supply VDDPLL PLL GND Ground ...
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Table 3-1. Signal Description List (Continued) Signal Name Function DDM USB Device Port Data - DDP USB Device Port Data + SCK0 - SCK1 Serial Clock TXD0 - TXD1 Transmit Data RXD0 - RXD1 Receive Data RTS0 - RTS1 Request ...
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Table 3-1. Signal Description List (Continued) Signal Name Function TWD Two-wire Serial Data TWCK Two-wire Serial Clock AD0-AD3 Analog Inputs AD4-AD7 Analog Inputs ADTRG ADC Trigger ADVREF ADC Reference PGMEN0-PGMEN2 Programming Enabling PGMM0-PGMM3 Programming Mode PGMD0-PGMD15 Programming Data PGMRDY Programming ...
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Package and Pinout The AT91SAM7S512/256/128/64/321 are available in a 64-lead LQFP or 64-pad QFN package. The AT91SAM7S161 is available in a 64-Lead LQFP package. The AT91SAM7S32/16 are available in a 48-lead LQFP or 48-pad QFN package. 4.1 64-lead LQFP ...
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LQFP and 64-pad QFN Pinout Table 4-1. AT91SAM7S512/256/128/64/321/161 Pinout 1 ADVREF 17 2 GND 18 3 AD4 19 4 AD5 20 5 AD6 21 6 AD7 22 7 VDDIN 23 8 VDDOUT 24 9 PA17/PGMD5/AD0 25 10 PA18/PGMD6/AD1 ...
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LQFP and 48-pad QFN Package Outlines Figure 4-3 age. A detailed mechanical description is given in the section Mechanical Characteristics of the full datasheet. Figure 4-3. Figure 4-4. 4.4 48-lead LQFP and 48-pad QFN Pinout Table 4-2. AT91SAM7S32/16 ...
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Power Considerations 5.1 Power Supplies The AT91SAM7S Series has six types of power supply pins and integrates a voltage regulator, allowing the device to be supplied with only one voltage. The six power supply pin types are: • VDDIN ...
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Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in parallel: 100 ...
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I/O Lines Considerations 6.1 JTAG Port Pins TMS, TDI and TCK are schmitt trigger inputs. TMS and TCK are 5-V tolerant, TDI is not. TMS, TDI and TCK do not integrate a pull-up resistor. TDO is an output, driven ...
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I/O line to VDDIO. Care should be taken, in particular at reset, as all the I/O lines default to input with the pull-up resistor enabled at reset. 6.6 I/O Line Drive Levels The PIO lines PA0 to ...
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Processor and Architecture 7.1 ARM7TDMI Processor • RISC processor based on ARMv4T Von Neumann architecture – Runs MHz, providing 0.9 MIPS/MHz • Two instruction sets – ARM – Thumb • Three-stage pipeline architecture – Instruction ...
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Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required – Key-protected program, erase and lock/unlock sequencer – Single command for erasing, programming and locking operations – Interrupt generation in case of forbidden operation 7.4 Peripheral DMA Controller ...
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Memories 8.1 AT91SAM7S512 • 512 Kbytes of Flash Memory, dual plane – 2 contiguous banks of 1024 pages of 256 bytes – Fast access time, 30 MHz single-cycle access in Worst Case conditions – Page programming time: 6 ms, ...
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AT91SAM7S64 • 64 Kbytes of Flash Memory, single plane – 512 pages of 128 bytes – Fast access time, 30 MHz single-cycle access in Worst Case conditions – Page programming time: 6 ms, including page auto-erase – Page programming ...
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Figure 8-1. AT91SAM7S512/256/128/64/321/32/161/16 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256 MBytes 0x0FFF FFFF 0x1000 0000 Undefined 14 x 256 MBytes (Abort) 3,584 MBytes 0xEFFF FFFF 0xF000 0000 Internal Peripherals 256M Bytes 0xFFFF FFFF AT91SAM7S Series Preliminary 20 ...
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Memory Mapping 8.7.1 Internal SRAM • The AT91SAM7S512 embeds a high-speed 64-Kbyte SRAM bank. • The AT91SAM7S256 embeds a high-speed 64-Kbyte SRAM bank. • The AT91SAM7S128 embeds a high-speed 32-Kbyte SRAM bank. • The AT91SAM7S64 embeds a high-speed 16-Kbyte ...
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Embedded Flash 8.8.1 Flash Overview • The Flash of the AT91SAM7S512 is organized in two banks (dual plane) of 1024 pages of 256 bytes. The 524,288 bytes are organized in 32-bit words. • The Flash of the AT91SAM7S256 is ...
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Lock Regions 8.8.3.1 AT91SAM7S512 Two Embedded Flash Controllers each manage 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7S512 contains 32 lock regions and each lock region contains 64 ...
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If a locked-region’s erase or program command occurs, the command is aborted and the LOCKE bit in the MC_FSR register rises and the interrupt line rises if the LOCKE bit has been written the MC_FMR register. The ...
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Security Bit Feature The AT91SAM7S Series features a security bit, based on a specific NVM Bit. When the security is enabled, any access to the Flash, either through the ICE interface or through the Fast Flash Programming Interface, is ...
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The SAM-BA Boot Assistant is a default Boot Program that provides an easy way to program in situ the on-chip Flash memory. The SAM-BA Boot Assistant supports serial communication through the DBGU or through the USB Device Port. (The AT91SAM7S32/16 ...
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Figure 9-1. System Controller Block Diagram (AT91SAM7S512/256/128/64/321/161) irq0-irq1 periph_irq[2..14] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq MCK periph_nreset dbgu_rxd MCK debug power_on_reset SLCK power_on_reset SLCK debug proc_nreset cal gpnvm[0] en BOD POR NRST SLCK SLCK RCOSC XIN MAINCK OSC XOUT PLL ...
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Figure 9-2. System Controller Block Diagram (AT91SAM7S32/16) irq0 fiq periph_irq[2..14] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq MCK periph_nreset dbgu_rxd MCK debug periph_nreset SLCK power_on_reset SLCK debug idle proc_nreset cal gpnvm[0] en BOD POR NRST SLCK SLCK RCOSC XIN MAINCK OSC ...
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Reset Controller The Reset Controller is based on a power-on reset cell and one brownout detector. It gives the status of the last reset, indicating whether power-up reset, a software reset, a user reset, a watchdog ...
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Clock Generator The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics: • RC Oscillator ranges between 22 kHz and 42 kHz • Main Oscillator frequency ranges between 3 and 20 ...
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Figure 9-4. 9.4 Advanced Interrupt Controller • Controls the interrupt lines (nIRQ and nFIQ ARM Processor • Individually maskable and vectored interrupt sources – Source 0 is reserved for the Fast Interrupt Input (FIQ) – Source 1 is ...
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Debug Unit • Comprises: – One two-pin UART – One Interface for the Debug Communication Channel (DCC) support – One set of Chip ID Registers – One Interface providing ICE Access Prevention • Two-pin UART – Implemented features are ...
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Real-time Timer • 32-bit free-running counter with alarm running on prescaled SCLK • Programmable 16-bit prescaler for SLCK accuracy compensation 9.9 PIO Controller • One PIO Controller, controlling 32 I/O lines (21 for AT91SAM7S32/16) • Fully programmable through set/clear ...
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Peripherals 10.1 User Interface The User Peripherals are mapped in the 256 MBytes of address space between 0xF000 0000 and 0xFFFF EFFF. Each peripheral is allocated 16 Kbytes of address space. A complete memory map is provided in 10.2 ...
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Table 10-2. Peripheral Note: 10.3 Peripheral Multiplexing on PIO Lines The AT91SAM7S Series features one PIO controller, PIOA, that ...
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PIO Controller A Multiplexing Table 10-3. Multiplexing on PIO Controller A (AT91SAM7S512/256/128/64/321/161) PIO Controller A I/O Line Peripheral A PA0 PWM0 PA1 PWM1 PA2 PWM2 PA3 TWD PA4 TWCK PA5 RXD0 PA6 TXD0 PA7 RTS0 PA8 CTS0 PA9 DRXD ...
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Table 10-4. Multiplexing on PIO Controller A (AT91SAM7S32/16) PIO Controller A I/O Line Peripheral A PA0 PWM0 PA1 PWM1 PA2 PWM2 PA3 TWD PA4 TWCK PA5 RXD0 PA6 TXD0 PA7 RTS0 PA8 CTS0 PA9 DRXD PA10 DTXD PA11 NPCS0 PA12 ...
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Serial Peripheral Interface • Supports communication with external serial devices – Four chip selects with external decoder allow communication with – Serial memories, such as DataFlash – Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN ...
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ISO7816 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • IrDA modulation and demodulation – Communication 115.2 Kbps • Test Modes ...
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PWM Controller • Four channels, one 16-bit counter per channel • Common clock generator, providing thirteen different clocks – One Modulo n counter providing eleven clocks – Two independent linear dividers working on modulo n counter outputs • Independent ...
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ARM7TDMI Processor Overview 11.1 Overview The ARM7TDMI core executes both the 32-bit ARM ing the user to trade off between high performance and high code density.The ARM7TDMI processor implements Von Neuman architecture, using a three-stage pipeline consisting of Fetch, ...
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ARM7TDMI Processor For further details on ARM7TDMI, refer to the following ARM documents: ARM Architecture Reference Manual (DDI 0100E) ARM7TDMI Technical Reference Manual (DDI 0210B) 11.2.1 Instruction Type Instructions are either 32 bits long (in ARM state ...
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Table 11-1. User and System Mode R10 R11 R12 R13 R14 PC CPSR Registers are unbanked registers. This means that each of them refers to the same ...
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A seventh processing mode, System Mode, does not have any banked registers. It uses the User Mode registers. System Mode runs tasks that require a privileged processor mode and allows them to invoke all classes of exceptions. 11.2.4.2 Status Registers ...
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Table 11-2. Mnemonic MOV ADD SUB RSB CMP TST AND EOR MUL SMULL SMLAL MSR B BX LDR LDRSH LDRSB LDRH LDRB LDRBT LDRT LDM SWP MCR LDC 11.2.6 Thumb Instruction Set Overview The Thumb instruction set is a re-encoded ...
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Stack Pointer (ARM Register 13). Further instructions allow limited access to the ARM registers 8 to 15. Table 11-3 Table 11-3. Mnemonic MOV ADD SUB CMP TST AND EOR LSL ASR MUL B BX LDR LDRH LDRB LDRSH LDMIA PUSH ...
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Debug and Test Features 12.1 Description The AT91SAM7S Series Microcontrollers feature a number of complementary debug and test capabilities. A common JTAG/ICE (EmbeddedICE) port is used for standard debugging func- tions, such as downloading code and single-stepping through programs. ...
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Application Examples 12.3.1 Debug Environment Figure 12-2 on page 48 face is used for standard debugging functions, such as downloading code and single-stepping through the program. Figure 12-2. Application Debug Environment Example AT91SAM7S Series Preliminary 48 shows a complete ...
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Test Environment Figure 12-3 on page 49 preted by the tester. In this example, the “board in test” is designed using a number of JTAG- compliant devices. These devices can be connected to form a single scan chain. Figure ...
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Debug and Test Pin Description Table 12-1. Pin Name NRST TST TCK TDI TDO TMS JTAGSEL DRXD DTXD AT91SAM7S Series Preliminary 50 Debug and Test Pin List Function Reset/Test Microcontroller Reset Test Mode Select ICE and JTAG Test Clock ...
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Functional Description 12.5.1 Test Pin One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with ...
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Table 12-2. AT91SAM7S64 Rev C AT91SAM7S128 Rev A AT91SAM7S128 Rev B AT91SAM7S128 Rev C AT91SAM7S256 Rev A AT91SAM7S256 Rev B AT91SAM7S256 Rev C AT91SAM7S512 Rev A and B For further details on the Debug Unit, see the Debug Unit section. ...
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Table 12-3. Bit Number 6175K–ATARM–30-Aug-10 AT91SAM7S Series Preliminary AT91SAM7Sxx JTAG Boundary Scan Register (Continued) Pin Name 90 89 PA21/PGMD9 PA19/PGMD7/AD2 PA20/PGMD8/AD3 PA16/PGMD4 PA15/PGM3 PA14/PGMD2 73 ...
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Table 12-3. Bit Number AT91SAM7S Series Preliminary 54 AT91SAM7Sxx JTAG Boundary Scan Register (Continued) Pin Name 57 56 PA11/PGMM3 PA10/PGMM2 PA9/PGMM1 PA8/PGMM0 PA7/PGMNVALID PA6/PGMNOE 40 ...
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Table 12-3. Bit Number Note: 6175K–ATARM–30-Aug-10 AT91SAM7S Series Preliminary AT91SAM7Sxx JTAG Boundary Scan Register (Continued) Pin Name 24 23 PA28 PA3 PA2 PA1/PGMEN1 PA0/PGMEN0 PA29 ...
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ID Code Register Access: Read-only 31 30 VERSION PART NUMBER 7 6 The JTAG D is used in the IEEE 1149.1 JTAG Boundary Scan. • VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: ...
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Reset Controller (RSTC) 13.1 Overview The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the sys- tem without any external components. It reports which reset occurred last. The Reset Controller also drives independently or ...
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Functional Description 13.3.1 Reset Controller Overview The Reset Controller is made NRST Manager, a Brownout Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: • ...
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NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in ...
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Reset States The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed ...
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User Reset The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR The NRST input signal is resynchronized with SLCK to insure proper behav- ior ...
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Brownout Reset When the brown_out/bod_reset signal is asserted, the Reset State Manager immediately enters the Brownout Reset. In this state, the processor, the peripheral and the external reset lines are asserted. The Brownout Reset is left Y Slow Clock ...
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Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: • PROCRST: Writing PROCRST at 1 resets the ...
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Figure 13-7. Software Reset 13.3.4.5 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts Y Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR: ...
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Figure 13-8. Watchdog Reset Only if WDRPROC = 0 6175K–ATARM–30-Aug-10 AT91SAM7S Series Preliminary SLCK Any MCK Freq. wd_fault proc_nreset RSTTYP Any periph_nreset NRST (nrst_out) Processor Startup = 3 cycles XXX 0x2 = Watchdog Reset EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) ...
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Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: • Power-up Reset • Brownout Reset • Watchdog Reset • Software Reset • User Reset Particular cases are listed ...
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Figure 13-9. Reset Controller Status and Interrupt MCK Peripheral Access 2 cycle resynchronization NRST NRSTL URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) 6175K–ATARM–30-Aug-10 AT91SAM7S Series Preliminary read RSTC_SR 2 cycle resynchronization 67 ...
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Reset Controller (RSTC) User Interface Table 13-1. Register Mapping Offset Register 0x00 Control Register 0x04 Status Register 0x08 Mode Register AT91SAM7S Series Preliminary 68 Name Access RSTC_CR Write-only RSTC_SR Read-only RSTC_MR Read-write Reset - 0x0000_0000 0x0000_0000 6175K–ATARM–30-Aug-10 ...
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Reset Controller Control Register Register Name: RSTC_CR Access Type: Write-only – – – – – – • PROCRST: Processor Reset effect KEY is correct, resets ...
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Reset Controller Status Register Register Name: RSTC_SR Access Type: Read-only 31 30 – – – – – – – – • URSTS: User Reset Status high-to-low edge on NRST happened ...
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Reset Controller Mode Register Register Name: RSTC_MR Access Type: Read/Write – – – – – – • URSTEN: User Reset Enable 0 = The detection of a low level on the ...
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AT91SAM7S Series Preliminary 72 6175K–ATARM–30-Aug-10 ...
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Real-time Timer (RTT) 14.1 Overview The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It gen- erates a periodic interrupt or/and triggers an alarm on a programmed value. 14.2 Block Diagram Figure 14-1. ...
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The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As this value can be updated asynchronously from the Master Clock advis- able to read this register twice at the ...
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Real-time Timer (RTT) User Interface Table 14-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Alarm Register 0x08 Value Register 0x0C Status Register 6175K–ATARM–30-Aug-10 AT91SAM7S Series Preliminary Name Access RTT_MR Read-write RTT_AR Read-write RTT_VR Read-only RTT_SR Read-only Reset 0x0000_8000 ...
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Real-time Timer Mode Register Register Name: RTT_MR Access Type: Read-write 31 30 – – – – • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the real-time ...
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Real-time Timer Alarm Register Register Name: RTT_AR Access Type: Read-write • ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer. 6175K–ATARM–30-Aug-10 AT91SAM7S Series Preliminary ...
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Real-time Timer Value Register Register Name: RTT_VR Access Type: Read-only • CRTV: Current Real-time Value Returns the current value of the Real-time Timer. AT91SAM7S Series Preliminary CRTV ...
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Real-time Timer Status Register Register Name: RTT_SR Access Type: Read-only 31 30 – – – – – – – – • ALMS: Real-time Alarm Status 0 = The Real-time Alarm has not occurred ...
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AT91SAM7S Series Preliminary 80 6175K–ATARM–30-Aug-10 ...
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Periodic Interval Timer (PIT) 15.1 Overview The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt designed to offer maximum accuracy and efficient management, even for systems with long response time. 15.2 Block Diagram Figure 15-1. ...
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Functional Description The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature built around two counters: a 20-bit CPIV counter and a ...
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Figure 15-2. Enabling/Disabling PIT with PITEN 15 MCK Prescaler 0 PITEN CPIV 0 PICNT PITS (PIT_SR) APB Interface 6175K–ATARM–30-Aug-10 AT91SAM7S Series Preliminary MCK 1 PIV - 1 PIV 1 0 read PIT_PIVR APB cycle APB cycle restarts MCK Prescaler 0 ...
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Periodic Interval Timer (PIT) User Interface Table 15-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Status Register 0x08 Periodic Interval Value Register 0x0C Periodic Interval Image Register AT91SAM7S Series Preliminary 84 Name Access PIT_MR Read-write PIT_SR Read-only PIT_PIVR ...
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Periodic Interval Timer Mode Register Register Name: PIT_MR Access Type: Read-write 31 30 – – – – • PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the ...
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Periodic Interval Timer Status Register Register Name: PIT_SR Access Type: Read-only 31 30 – – – – – – – – • PITS: Periodic Interval Timer Status 0 = The Periodic Interval timer ...
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Periodic Interval Timer Value Register Register Name: PIT_PIVR Access Type: Read-only PICNT Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value of the ...
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Periodic Interval Timer Image Register Register Name: PIT_PIIR Access Type: Read-only PICNT • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval ...
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Watchdog Timer (WDT) 16.1 Overview The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period seconds ...
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Functional Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a ...
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Figure 16-2. Watchdog Behavior FFF Normal behavior WDV Forbidden Window WDD Permitted Window 0 Watchdog Fault 6175K–ATARM–30-Aug-10 AT91SAM7S Series Preliminary Watchdog Error WDT_CR = WDRSTT Watchdog Underflow if WDRSTEN WDRSTEN ...
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Watchdog Timer (WDT) User Interface Table 16-1. Register Mapping Offset Register 0x00 Control Register 0x04 Mode Register 0x08 Status Register 16.4.1 Watchdog Timer Control Register Register Name: WDT_CR Access Type: Write-only – – ...
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Watchdog Timer Mode Register Register Name: WDT_MR Access Type: Read-write Once 31 30 – – WDIDLEHLT WDDIS WDRPROC WDRSTEN 7 6 • WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter. ...
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WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer. 16.4.3 Watchdog Timer Status Register Register Name: WDT_SR Access Type: Read-only 31 30 – – – – – – – ...
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Voltage Regulator Mode Controller (VREG) 17.1 Overview The Voltage Regulator Mode Controller contains one Read/Write register, the Voltage Regulator Mode Register. Its offset is 0x60 with respect to the System Controller offset. This register controls the Voltage Regulator Mode. ...
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Voltage Regulator Power Controller (VREG) User Interface Table 17-1. Register Mapping Offset Register 0x60 Voltage Regulator Mode Register 17.2.1 Voltage Regulator Mode Register Register Name: VREG_MR Access Type: Read-write 31 30 – – – – ...
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Memory Controller (MC) 18.1 Overview The Memory Controller (MC) manages the ASB bus and controls accesses requested by the masters, typically the ARM7TDMI processor and the Peripheral DMA Controller. It features a simple bus arbiter, an address decoder, an ...
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Functional Description The Memory Controller handles the internal ASB bus and arbitrates the accesses of both masters made up of: • A bus arbiter • An address decoder • An abort status • A misalignment detector • ...
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Internal Memory Mapping Within the Internal Memory address space, the Address Decoder of the Memory Controller decodes eight more address bits to allocate 1-Mbyte address spaces for the embedded memories. The allocated memories are accessed all along the 1-Mbyte ...
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Abort Status There are three reasons for an abort to occur: • access to an undefined address • an access to a misaligned address. When an abort occurs, a signal is sent back to all the masters, regardless of ...
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As the requested address is saved in the Abort Status Register and the address of the instruc- tion generating the misalignment is saved in the Abort Link Register of the processor, detection and fix of this kind of software bug ...
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MC Remap Control Register Register Name: MC_RCR Access Type: Write-only Offset: 0x00 31 30 – – – – – – – – • RCB: Remap Command Bit 0: No effect. 1: This Command ...
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MC Abort Status Register Register Name: MC_ASR Access Type: Read-only Reset Value: 0x0 Offset: 0x04 31 30 – – – – – – – – • UNDADD: Undefined Address Abort Status 0: The ...
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MST1: ARM7TDMI Abort Source 0: The last aborted access was not due to the ARM7TDMI. 1: The last aborted access was due to the ARM7TDMI. • SVMST0: Saved PDC Abort Source 0: No abort due to the PDC occurred. ...
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Embedded Flash Controller (EFC) 19.1 Overview The Embedded Flash Controller (EFC ) is a part of the Memory Controller and ensures the inter- face of the Flash block with the 32-bit internal bus. It increases performance in Thumb Mode ...
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Figure 19-1. Embedded Flash Memory Mapping AT91SAM7S Series Preliminary 106 Flash Memory Start Address Lock Region 0 Lock Region 1 Lock Region (n-1) 32-bit wide Page 0 Lock Bit 0 Page (m-1) Lock Bit 1 Page ( (n-1)*m ) Lock ...
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Read Operations An optimized controller manages embedded Flash reads. A system 32-bit buffers is added in order to start access at following address during the second read, thus increasing perfor- mance when the processor is running ...
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Note: When FWS is equal case of sequential reads, all the accesses are performed in a single-cycle access (except for the first one). Figure 19-4. Code Read Optimization in Thumb Mode for FWS = 3 3 Wait ...
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Write Operations The internal memory area reserved for the embedded Flash can also be written through a write- only latch buffer. Write operations take into account only the 8 lowest address bits and thus wrap around within the internal ...
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Figure 19-5. Command State Chart In order to guarantee valid operations on the Flash memory, the field Flash Microsecond Cycle Number (FMCN) in the Flash Mode Register MC_FMR must be correctly programmed (see Flash Mode Register” on page 19.2.4.1 Flash ...
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Figure 19-6. Example of Partial Page Programming 32 bits wide ... 16 words ... 16 words ...
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Erase All operation is allowed only if there are no lock bits set. Thus least one lock region is locked, the bit LOCKE in MC_FSR rises and the command is cancelled. If the bit LOCKE has been written ...
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General-purpose NVM Bits General-purpose NVM bits do not interfere with the embedded Flash memory plane. (Does not apply to EFC1 on the AT91SAM7S512.) These general-purpose bits are dedicated to protect other parts of the product. They can be set ...
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When the locking completes, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated. When the ...
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Embedded Flash Controller (EFC) User Interface The User Interface of the EFC is integrated within the Memory Controller with Base Address: 0xFFFF FF00. The AT91SAM7S512 is equipped with two EFCs, EFC0 and EFC1, as described in the Register Mapping ...
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MC Flash Mode Register Register Name: MC_FMR Access Type: Read-write Offset: (EFC0) 0x60 Offset: (EFC1) 0x70 31 30 – – – – NEBP – • FRDY: Flash Ready Interrupt Enable 0: Flash Ready ...
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FMCN: Flash Microsecond Cycle Number Before writing Non Volatile Memory bits (Lock bits, General Purpose NVM bit and Security bits), this field must be set to the number of Master Clock cycles in one microsecond. When writing the rest ...
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MC Flash Command Register Register Name: MC_FCR Access Type: Write-only Offset: (EFC0) 0x64 Offset: (EFC1) 0x74 – – – – • FCMD: Flash Command This field defines the Flash commands: FCMD ...
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PAGEN: Page Number Command Write Page Command Write Page and Lock Command Erase All Command Set/Clear Lock Bit Command Set/Clear General Purpose NVM Bit Command Set Security Bit Command Note: Depending on the command, all the possible unused bits ...
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MC Flash Status Register Register Name: MC_FSR Access Type: Read-only Offset: (EFC0) 0x68 Offset: (EFC1) 0x78 31 30 LOCKS15 LOCKS14 LOCKS13 23 22 LOCKS7 LOCKS6 15 14 – – – – • FRDY: Flash Ready Status 0: ...
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MC_FSR, LOCKSx Product Specific Map AT91SAM7S AT91SAM7S AT91SAM7S 512 256 128 () 32 16 LOCKS0 LOCKS0 LOCKS0 LOCKS1 LOCKS1 LOCKS1 LOCKS2 LOCKS2 LOCKS2 LOCKS3 LOCKS3 LOCKS3 LOCKS4 LOCKS4 LOCKS4 LOCKS5 LOCKS5 LOCKS5 LOCKS6 LOCKS6 LOCKS6 LOCKS7 LOCKS7 LOCKS7 LOCKS8 LOCKS8 ...
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AT91SAM7S Series Preliminary 122 6175K–ATARM–30-Aug-10 ...
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Fast Flash Programming Interface (FFPI) 20.1 Overview The Fast Flash Programming Interface provides two solutions - parallel or serial - for high-vol- ume programming using a standard gang programmer. The parallel interface is fully handshaked and the device is ...
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Parallel Fast Flash Programming 20.2.1 Device Configuration In Fast Flash Programming Mode, the device specific test mode. Only a certain set of pins is significant. Other pins must be left unconnected. Figure 20-1. AT91SAM7S512/256/128/64/321/161 Parallel Programming ...
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Table 20-1. Signal Description List Signal Name Function VDDFLASH Flash Power Supply VDDIO I/O Lines Power Supply VDDCORE Core Power Supply VDDPLL PLL Power Supply GND Ground Main Clock Input. XIN This input can be tied to GND. In this ...
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Signal Names Depending on the MODE settings, DATA is latched in different internal registers. Table 20-2. MODE[3:0] 0000 0001 0010 0011 0100 0101 Default When MODE is equal to CMDE, then a new command (strobed on DATA[15:0] or DATA[7:0] ...
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Entering Programming Mode The following algorithm puts the device in Parallel Programming Mode: • Apply GND, VDDIO, VDDCORE, VDDFLASH and VDDPLL. • Apply XIN clock within T • Wait for T • Start a read or write handshaking. Note: ...
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Figure 20-4. AT91SAM7S32/16 Parallel Programming Timing, Write Sequence NCMD RDY NOE NVALID DATA[7:0] MODE[3:0] Table 20-4. Write Handshake Step Programmer Action 1 Sets MODE and DATA signals 2 Clears NCMD signal 3 Waits for RDY low 4 Releases MODE and ...
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Figure 20-6. AT91SAM7S32/16 Parallel Programming Timing, Read Sequence NCMD RDY NOE NVALID DATA[7:0] MODE[3:0] Table 20-5. Read Handshake Step Programmer Action 1 Sets MODE and DATA signals 2 Clears NCMD signal 3 Waits for RDY low 4 Sets DATA signal ...
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Device Operations Several commands on the Flash memory are available. These commands are summarized in Table 20-3 on page face running several read/write handshaking sequences. When a new command is executed, the previous one is automatically achieved. Thus, chaining ...
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Table 20-7. Step n+1 n+2 n+3 n+4 n+5 ... 20.2.5.2 Flash Write Command This command is used to write the Flash contents. The Flash memory plane is organized into several pages. Data to be written are stored in a load ...
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Table 20-9. Step ... n n+1 n+2 n+3 n+4 n+5 ... The Flash command Write Page and Lock (WPL) is equivalent to the Flash Write Command. However, the lock bit is automatically set at the end of ...
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In the same way, the Clear Lock command (CLB) is used to clear lock bits. All the lock bits are also cleared by the EA command. Table 20-11. Set and Clear Lock Bit Command Step 1 2 Lock bits can ...
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The AT91SAM7S512 security bit is controlled by the EFC0. To use the Set Security Bit com- mand, the EFC0 must be selected using the Select EFC command Table 20-15. Set Security Bit Command Step 1 2 Once the security bit ...
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Table 20-17. Write Command (Continued) Step n+2 n+3 ... Table 20-18. Write Command Step ... n n+1 n+2 n+3 n+4 n+5 ... 20.2.5.9 Get Version Command The Get Version (GVE) command retrieves the ...
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Serial Fast Flash Programming The Serial Fast Flash programming interface is based on IEEE Std. 1149.1 “Standard Test Access Port and Boundary-Scan Architecture”. Refer to this standard for an explanation of terms used in this chapter and for a ...
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Table 20-20. Signal Description List (Continued) Signal Name Function TST Test Mode Select PGMEN0 Test Mode Select PGMEN1 Test Mode Select PGMEN2 Test Mode Select TCK JTAG TCK TDI JTAG Test Data In TDO JTAG Test Data Out TMS JTAG ...
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Read/Write Handshake The read/write handshake is done by carrying out read/write operations on two registers of the device that are accessible through the JTAG: • Debug Comms Control Register: DCCR • Debug Comms Data Register: DCDR Access to these ...
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Flash Read Command This command is used to read the Flash contents. The memory map is accessible through this command. Memory is seen as an array of words (32-bit wide). The read command can start at any valid address ...
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Flash Full Erase Command This command is used to erase the Flash memory planes. All lock bits must be deactivated before using the Full Erase command. This can be done by using the CLB command. Table 20-24. Full Erase ...
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GP NVM bits can be read using Get GPNVM Bit command (GGPB). When a bit set in the Bit Mask is returned, then the corresponding GPNVM bit is set. Table 20-28. Get General-purpose NVM Bit Command Read/Write Write Read 20.3.4.6 ...
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Memory Write Command This command is used to perform a write access to any memory location. The Memory Write command (WRAM) is optimized for consecutive writes. An internal address buffer is automatically increased. Table 20-31. Write Command Read/Write Write ...
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AT91SAM7 Boot Program 21.1 Description The Boot Program integrates different programs permitting download and/or upload into the different memories of the product. First, it initializes the Debug Unit serial port (DBGU) and the USB Device Port. SAM-BA DBGU serial ...
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Device Initialization with USB Initialization follows the steps described below: 1. FIQ initialization 1. Stack setup for ARM supervisor mode 2. Setup the Embedded Flash Controller 3. External Clock detection 4. Main oscillator frequency detection if no external clock ...
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SAM-BA Boot The SAM-BA boot principle is to: Figure 21-3. Auto Baudrate Flow Diagram 6175K–ATARM–30-Aug-10 AT91SAM7S Series Preliminary – Check if USB Device enumeration has occurred – Check if the Auto Baudrate sequence has succeeded (see Device Setup Character ...
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Once the communication interface is identified, the application runs in an infinite Table 21-1. Command • Write commands: Write a byte (O), a halfword ( word (W) ...
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DBGU Serial Port Communication is performed through the DBGU serial port initialized to 115200 Baud The Send and Receive File commands use the Xmodem protocol to communicate. Any termi- nal performing this protocol can be used ...
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... ISDN modems and virtual COM ports. The Vendor ID is Atmel’s vendor ID 0x03EB. The product ID is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence between vendor ID and product ID. ...
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Communication Endpoints There are two communication endpoints and endpoint 0 is used for the enumeration process. Endpoint 64-byte Bulk OUT endpoint and endpoint 64-byte Bulk IN endpoint. SAM-BA Boot commands are sent by ...
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Hardware and Software Constraints • SAM-BA boot copies itself in the SRAM and uses a block of internal SRAM for variables and stacks. The remaining available sizes for the user codes are as follows: 57344 bytes for AT91SAM7S512, 57344 ...
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Peripheral DMA Controller (PDC) 22.1 Overview The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals such as the UART, USART, SSC, SPI, MCI and the on- and off-chip memories. Using the Peripheral DMA Controller avoids processor intervention ...
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Functional Description 22.3.1 Configuration The PDC channels user interface enables the user to configure and control the data transfers for each channel. The user interface of a PDC channel is integrated into the user interface of the peripheral (offset ...
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Programming the Next Counter/Pointer registers chains the buffers. The counters are decre- mented after each data transfer as stated above, but when the transfer counter reaches zero, the values of the Next Counter/Pointer are loaded into the Counter/Pointer registers in ...
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Peripheral DMA Controller (PDC) User Interface Table 22-1. Register Mapping Offset Register 0x100 Receive Pointer Register 0x104 Receive Counter Register 0x108 Transmit Pointer Register 0x10C Transmit Counter Register 0x110 Receive Next Pointer Register 0x114 Receive Next Counter Register 0x118 ...
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PDC Receive Pointer Register Register Name: PERIPH_RPR Access Type: Read-write • RXPTR: Receive Pointer Address Address of the next receive transfer. 22.4.2 PDC Receive Counter Register Register Name: PERIPH_RCR Access Type: ...
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PDC Transmit Pointer Register Register Name: PERIPH_TPR Access Type: Read-write • TXPTR: Transmit Pointer Address Address of the transmit buffer. 22.4.4 PDC Transmit Counter Register Register Name: PERIPH_TCR Access Type: Read-write ...
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PDC Receive Next Pointer Register Register Name: PERIPH_RNPR Access Type: Read-write • RXNPTR: Receive Next Pointer Address RXNPTR is the address of the next buffer to fill with received data when ...
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PDC Transmit Next Pointer Register Register Name: PERIPH_TNPR Access Type: Read-write • TXNPTR: Transmit Next Pointer Address TXNPTR is the address of the next buffer to transmit when the current buffer ...
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PDC Transfer Control Register Register Name: PERIPH_PTCR - Access Type: Write only 31 30 – – – – – – – – • RXTEN: Receiver Transfer Enable effect ...
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PDC Transfer Status Register Register Name: PERIPH_PTSR Access Type: Read-only 31 30 – – – – – – – – • RXTEN: Receiver Transfer Enable 0 = Receiver PDC transfer requests are disabled. ...
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Advanced Interrupt Controller (AIC) 23.1 Overview The Advanced Interrupt Controller (AIC 8-level priority, individually maskable, vectored interrupt controller, providing handling thirty-two interrupt sources designed to sub- stantially reduce the software and real-time ...
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Application Block Diagram Figure 23-2. Description of the Application Block 23.4 AIC Detailed Block Diagram Figure 23-3. AIC Detailed Block Diagram 23.5 I/O Line Description Table 23-1. I/O Line Description Pin Name FIQ IRQ0 - IRQn AT91SAM7S Series Preliminary ...
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Product Dependencies 23.6.1 I/O Lines The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO control- lers. Depending on the features of the PIO controller used in the product, the pins must be programmed in ...
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Functional Description 23.7.1 Interrupt Source Control 23.7.1.1 Interrupt Source Mode The Advanced Interrupt Controller independently programs each interrupt source. The SRC- TYPE field of the corresponding AIC_SMR (Source Mode Register) selects the interrupt condition of each source. The internal ...
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Internal Interrupt Source Input Stage Figure 23-4. 23.7.1.6 External Interrupt Source Input Stage Figure 23-5. External Interrupt Source Input Stage Source i AIC_ISCR AIC_ICCR 6175K–ATARM–30-Aug-10 AT91SAM7S Series Preliminary Internal Interrupt Source Input Stage AIC_SMRI (SRCTYPE) Level/ Source i Edge ...
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Interrupt Latencies Global interrupt latencies depend on several parameters, including: • The time the software masks the interrupts. • Occurrence, either at the processor level or at the AIC level. • The execution time of the instruction in progress ...
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External Interrupt Level Sensitive Source Figure 23-7. 23.7.2.3 Internal Interrupt Edge Triggered Source Figure 23-8. 23.7.2.4 Internal Interrupt Level Sensitive Source Figure 23-9. 6175K–ATARM–30-Aug-10 AT91SAM7S Series Preliminary External Interrupt Level Sensitive Source MCK IRQ or FIQ (High Level) IRQ ...
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Normal Interrupt 23.7.3.1 Priority Controller An 8-level priority controller drives the nIRQ line of the processor, depending on the interrupt conditions occurring on the interrupt sources (except for those programmed in Fast Forcing). Each interrupt source ...
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When the processor executes this instruction, it loads the read value in AIC_IVR in its program counter, thus branching the execution on the correct interrupt handler. This feature is often not used when the application is based on an operating ...
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Further interrupts can then be unmasked by clearing the “I” bit in CPSR, allowing re- assertion of the nIRQ to be taken into account by the core. This can happen if an inter- rupt with a higher priority than ...
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Fast Interrupt 23.7.4.1 Fast Interrupt Source The interrupt source 0 is the only source which can raise a fast interrupt request to the processor except if fast forcing is used. The interrupt source 0 is generally connected to a ...
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In this case only, it de-asserts the nFIQ line on the processor. 4. The previous step enables branching to the corresponding interrupt service routine ...
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All enabled and pending interrupt sources that have the fast forcing feature enabled and that are programmed in edge-triggered mode must be cleared by writing to the Interrupt Clear Command Register. In doing so, they are cleared independently and thus ...
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Protect Mode The Protect Mode permits reading the Interrupt Vector Register without performing the associ- ated automatic operations. This is necessary when working with a debug system. When a debugger, working either with a Debug Monitor or the ARM ...
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An internal interrupt source is programmed in level sensitive and the output signal of the corresponding embedded peripheral is activated for a short time. (As in the case for the Watchdog.) • An interrupt occurs just a few cycles ...
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Advanced Interrupt Controller (AIC) User Interface 23.8.1 Base Address The AIC is mapped at the address 0xFFFF F000. It has a total 4-Kbyte addressing space. This permits the vectoring fea- ture, as the PC-relative load/store instructions of the ARM ...
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AIC Source Mode Register Register Name: AIC_SMR0..AIC_SMR31 Access Type: Read/Write Reset Value: 0x0 31 30 – – – – – – – SRCTYPE • PRIOR: Priority Level Programs the priority level for all ...
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AIC Source Vector Register Register Name: AIC_SVR0..AIC_SVR31 Access Type: Read/Write Reset Value: 0x0 • VECTOR: Source Vector The user may store in these registers the addresses of the corresponding handler for ...
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AIC FIQ Vector Registe Register Name: AIC_FVR Access Type: Read-only Reset Value • FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in ...
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AIC Interrupt Pending Register Register Name: AIC_IPR Access Type: Read-only Reset Value: 0x0 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • FIQ, SYS, PID2-PID31: Interrupt Pending 0 = Corresponding interrupt ...
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AIC Core Interrupt Status Register Register Name: AIC_CISR Access Type: Read-only Reset Value: 0x0 31 30 – – – – – – – – • NFIQ: NFIQ Status 0 = nFIQ line is ...
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AIC Interrupt Disable Command Register Register Name: AIC_IDCR Access Type: Write-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • FIQ, SYS, PID2-PID31: Interrupt Disable effect ...
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AIC Interrupt Set Command Register Register Name: AIC_ISCR Access Type: Write-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • FIQ, SYS, PID2-PID31: Interrupt Set effect ...
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AIC Spurious Interrupt Vector Register Register Name: AIC_SPU Access Type: Read/Write Reset Value: 0x0 • SIVR: Spurious Interrupt Vector Register The user may store the address of a spurious interrupt handler ...
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AIC Fast Forcing Enable Register Register Name: AIC_FFER Access Type: Write-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • SYS, PID2-PID31: Fast Forcing Enable effect ...
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AIC Fast Forcing Status Register Register Name: AIC_FFSR Access Type: Read-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • SYS, PID2-PID31: Fast Forcing Status 0 = The Fast Forcing feature ...
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Clock Generator 24.1 Overview The Clock Generator is made PLL, a Main Oscillator, as well Oscillator. It provides the following clocks: • SLCK, the Slow Clock, which is the only permanent clock within ...
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Figure 24-2. Typical Crystal Connection 24.3.2 Main Oscillator Startup Time The startup time of the Main Oscillator is given in the DC Characteristics section of the product datasheet. The startup time depends on the crystal frequency and decreases when the ...
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Slow Clock, so that the frequency of the crystal connected on the Main Oscillator can be determined. 24.3.5 Main Oscillator Bypass The user can input a clock on the device instead of connecting a crystal. In this case, the user ...
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... The user has to load the number of Slow Clock cycles required to cover the PLL transient time into the PLLCOUNT field. The transient time depends on the PLL filter. The initial state of the PLL and its target frequency can be calculated using a specific tool provided by Atmel. AT91SAM7S Series Preliminary 190 ...
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Power Management Controller (PMC) 25.1 Description The Power Management Controller (PMC) optimizes power consumption by controlling all sys- tem and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the ARM Processor. The ...
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Processor Clock Controller The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle Mode. The Processor Clock can be disabled by writing the System Clock Disable Register (PMC_SCDR). The status of this clock (at least for ...
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The bit number within the Peripheral Clock Control registers (PMC_PCER, PMC_PCDR, and PMC_PCSR) is the Peripheral Identifier defined at the product level. Generally, the bit number corresponds to the interrupt source number assigned to the peripheral. 25.6 Programmable Clock Output ...
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The DIV field is used to control divider itself. A value between 0 and 255 can be pro- grammed. Divider output is divider input divided by DIV parameter. By default DIV parameter is set to 0 which means that divider ...
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Program the CSS field in the PMC_MCKR register. – Wait for the MCKRDY bit to be set in the PMC_SR register. • new value for CSS field corresponds to Main Clock or Slow Clock, – Program the ...
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PCKRDYx has been enabled in the PMC_IER register. All parameters in PMC_PCKx can be programmed in a single write operation. If the CSS and PRES parameters are to be modified, ...
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Clock Switching Details 25.8.1 Master Clock Switching Timings Table 25-1 selected clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64 clock cycles of the ...
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Figure 25-4. Switch Master Clock from Main Clock to Slow Clock Write PMC_MCKR Figure 25-5. Change PLL Programming Write CKGR_PLLR AT91SAM7S Series Preliminary 198 Slow Clock Main Clock MCKRDY Master Clock Main Clock PLL Clock LOCK MCKRDY Master Clock Main ...
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Figure 25-6. Programmable Clock Output Programming Write PMC_PCKx Write PMC_SCER Write PMC_SCDR 6175K–ATARM–30-Aug-10 AT91SAM7S Series Preliminary PLL Clock PCKRDY PCKx Output PLL Clock is selected PCKx is enabled PCKx is disabled 199 ...
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Power Management Controller (PMC) User Interface Table 25-2. Register Mapping Offset Register 0x0000 System Clock Enable Register 0x0004 System Clock Disable Register 0x0008 System Clock Status Register 0x000C Reserved 0x0010 Peripheral Clock Enable Register 0x0014 Peripheral Clock Disable Register ...