AT91SAM7S32B-MU Atmel, AT91SAM7S32B-MU Datasheet - Page 189
![IC MCU ARM7 32KB FLASH 48-VQFN](/photos/7/34/73471/48-vqfn-6_543-5130_01-4_sml.jpg)
AT91SAM7S32B-MU
Manufacturer Part Number
AT91SAM7S32B-MU
Description
IC MCU ARM7 32KB FLASH 48-VQFN
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7S16-MU.pdf
(779 pages)
Specifications of AT91SAM7S32B-MU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Manufacturer
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24.3.5
24.4
24.4.1
6175K–ATARM–30-Aug-10
Divider and PLL Block
Main Oscillator Bypass
PLL Filter
Slow Clock, so that the frequency of the crystal connected on the Main Oscillator can be
determined.
The user can input a clock on the device instead of connecting a crystal. In this case, the user
has to provide the external clock signal on the XIN pin. The input characteristics of the XIN pin
under these conditions are given in the product electrical characteristics section. The program-
mer has to be sure to set the OSCBYPASS bit to 1 and the MOSCEN bit to 0 in the Main OSC
register (CKGR_MOR) for the external clock to operate properly.
The PLL embeds an input divider to increase the accuracy of the resulting clock signals. How-
ever, the user must respect the PLL minimum input frequency when programming the divider.
Figure 24-3
Figure 24-3. Divider and PLL Block Diagram
The PLL requires connection to an external second-order filter through the PLLRC pin.
24-4
Figure 24-4. PLL Capacitors and Resistors
Values of R, C1 and C2 to be connected to the PLLRC pin must be calculated as a function of
the PLL input frequency, the PLL output frequency and the phase margin. A trade-off has to be
found between output signal overshoot and startup time.
shows a schematic of these filters.
shows the block diagram of the divider and PLL block.
MAINCK
SLCK
C2
Divider
AT91SAM7S Series Preliminary
DIV
C1
R
PLLRC
GND
PLLCOUNT
Counter
PLLRC
PLL
MUL
PLL
PLL
OUT
LOCK
PLLCK
Figure
189
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