AT89C5122D-RDRUM Atmel, AT89C5122D-RDRUM Datasheet - Page 122
![IC 8051 MCU 32K CRAM USB 64-VQFP](/photos/6/81/68127/313-64-vqfp_sml.jpg)
AT89C5122D-RDRUM
Manufacturer Part Number
AT89C5122D-RDRUM
Description
IC 8051 MCU 32K CRAM USB 64-VQFP
Manufacturer
Atmel
Series
89Cr
Datasheet
1.AT89C5122D-PSTUM.pdf
(208 pages)
Specifications of AT89C5122D-RDRUM
Core Processor
8051
Core Size
8-Bit
Speed
48MHz
Connectivity
SmartCard, SPI, UART/USART, USB
Peripherals
LED, POR, WDT
Number Of I /o
46
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCUAT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-03 - KIT STARTER FOR MCU AT8XC5122/23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Other names
AT89C5122D-RDRUMTR
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AT83R5122, AT8xC5122/23
Table 74. USB Endpoint Interrupt Register - UEPINT (S:F8h read-only)
Reset Value = 0000 0000b
Number
Bit
7
6
5
4
3
2
1
0
7
-
Mnemonic Description
EP6INT
EP5INT
EP4INT
EP3INT
EP2INT
EP1INT
EP0INT
EP6INT
Bit
-
6
Reserved
The value read from these bits is always 0. Do not change this bit.
Endpoint 6 Interrupt
This bit is set by hardware when an interrupt has been detected on the endpoint 6.
The interrupt sources are part of UEPSTAX register and can be : TXCMP,
RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when
the EP6INTE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the interrupt sources are cleared.
Endpoint 5 Interrupt
This bit is set by hardware when an interrupt has been detected on the endpoint 5.
The interrupt sources are part of UEPSTAX register and can be : TXCMP,
RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when
the EP5INTE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the interrupt sources are cleared.
Endpoint 4 Interrupt
This bit is set by hardware when an interrupt has been detected on the endpoint 4.
The interrupt sources are part of UEPSTAX register and can be : TXCMP,
RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when
the EP4INTE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the interrupt sources are cleared.
Endpoint 3 Interrupt
This bit is set by hardware when an interrupt has been detected on the endpoint 3.
The interrupt sources are part of UEPSTAX register and can be : TXCMP,
RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when
the EP3INTE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the interrupt sources are cleared.
Endpoint 2 Interrupt
This bit is set by hardware when an interrupt has been detected on the endpoint 2.
The interrupt sources are part of UEPSTAX register and can be : TXCMP,
RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when
the EP2INTE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the interrupt sources are cleared.
Endpoint 1 Interrupt
This bit is set by hardware when an interrupt has been detected on the endpoint 1.
The interrupt sources are part of UEPSTAX register and can be : TXCMP,
RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when
the EP1INTE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the interrupt sources are cleared.
Endpoint 0 Interrupt
This bit is set by hardware when an interrupt has been detected on the endpoint 0.
The interrupt sources are part of UEPSTAX register and can be : TXCMP,
RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when
the EP0INTE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the interrupt sources are cleared.
EP5INT
5
EP4INT
4
EP3INT
3
EP2INT
2
EP1INT
1
4202F–SCR–07/2008
EP0INT
0
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