AT89C5122D-RDRUM Atmel, AT89C5122D-RDRUM Datasheet - Page 50

IC 8051 MCU 32K CRAM USB 64-VQFP

AT89C5122D-RDRUM

Manufacturer Part Number
AT89C5122D-RDRUM
Description
IC 8051 MCU 32K CRAM USB 64-VQFP
Manufacturer
Atmel
Series
89Cr
Datasheet

Specifications of AT89C5122D-RDRUM

Core Processor
8051
Core Size
8-Bit
Speed
48MHz
Connectivity
SmartCard, SPI, UART/USART, USB
Peripherals
LED, POR, WDT
Number Of I /o
46
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCUAT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-03 - KIT STARTER FOR MCU AT8XC5122/23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Other names
AT89C5122D-RDRUMTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT89C5122D-RDRUM
Manufacturer:
Atmel
Quantity:
10 000
50
AT83R5122, AT8xC5122/23
Table 27. Clock Configuration Register 1 - CKCON1 (S:AFh) only for AT8xC5122
Reset Value = XXXX XXX0b
Table 28. PLL Control Register - PLLCON (S:A3h)
Reset Value = 0000 0000b
Table 29. PLL Divider Register - PLLDIV (S:A4h)
Reset Value = 0000 0000b
Bit Number Bit Mnemonic Description
Bit Number Bit Mnemonic Description
Bit Number Bit Mnemonic Description
7 - 4
7 - 3
7 - 4
3 - 0
R3
7
7
7
-
-
3
0
2
1
0
PLOCK
R2
PLLEN
6
6
EXT48
6
SPIX2
-
-
R3:0
N3:0
-
-
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
SPI clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Cleared to bypass the 1/2 prescaler.
Set to select the 1/2 output for this peripheral.
Reserved
The value read from these bits is always 0. Do not set this bits.
External 48 MHz Enable Bit
Set this bit to select XTAL1 as USB clock.
Clear this bit to select PLL as USB clock.
SCIB clock is controlled by EXT48 bit and XTSCS bit.
PLL Enable bit
Set to enable the PLL.
Clear to disable the PLL.
PLL Lock Indicator
Set by hardware when PLL is locked
Clear by hardware when PLL is unlocked
PLL R Divider Bits
PLL N Divider Bits
R1
5
5
5
-
-
R0
4
4
4
-
-
N3
3
3
3
-
-
EXT48
N2
2
2
2
-
PLLEN
N1
1
1
1
-
4202F–SCR–07/2008
PLOCK
SPIX2
N0
0
0
0

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