ATMEGA3250PV-10AU Atmel, ATMEGA3250PV-10AU Datasheet - Page 361

• Manufacturer Part Number: ATMEGA3250PV-10AU
• Description: IC MCU AVR 32K FLASH 100-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA3250PV-10AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, UART, USI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Data Rom Size: 1 KB
• Operating Supply Voltage: 1.8 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• A/d Bit Size: 10 bit
• A/d Channels Available: 8
• Height: 1 mm
• Length: 14 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Width: 14 mm
• For Use With: ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK504 - STARTER KIT AVR EXP MOD 100P LCD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATMEGA3250PV-8AU; ATMEGA3250PV-8AU

8023F–AVR–07/09
22 JTAG Interface and On-chip Debug System ..................................... 223
23 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 229
24 Boot Loader Support – Read-While-Write Self-Programming ......... 256
21.4Starting a Conversion ..........................................................................................208
21.5Prescaling and Conversion Timing ......................................................................209
21.6Changing Channel or Reference Selection .........................................................211
21.7ADC Noise Canceler ...........................................................................................212
21.8ADC Conversion Result ......................................................................................216
21.9Register Description ............................................................................................218
22.1Features ..............................................................................................................223
22.2Overview .............................................................................................................223
22.3TAP – Test Access Port ......................................................................................223
22.4TAP Controller .....................................................................................................225
22.5Using the Boundary-scan Chain ..........................................................................226
22.6Using the On-chip Debug System .......................................................................226
22.7On-chip Debug Specific JTAG Instructions .........................................................227
22.8Using the JTAG Programming Capabilities .........................................................227
22.9Bibliography .........................................................................................................228
22.10Register Description ..........................................................................................228
23.1Features ..............................................................................................................229
23.2Overview .............................................................................................................229
23.3Data Registers .....................................................................................................229
23.4Boundary-scan Specific JTAG Instructions .........................................................231
23.5Boundary-scan Chain ..........................................................................................232
23.6ATmega325P/3250P Boundary-scan Order ........................................................241
23.7Boundary-scan Description Language Files ........................................................254
23.8Register Description ............................................................................................255
24.1Features ..............................................................................................................256
24.2Overview .............................................................................................................256
24.3Application and Boot Loader Flash Sections .......................................................256
24.4Read-While-Write and No Read-While-Write Flash Sections ..............................257
24.5Boot Loader Lock Bits .........................................................................................259
24.6Entering the Boot Loader Program ......................................................................261
24.7Addressing the Flash During Self-Programming .................................................261
24.8Self-Programming the Flash ................................................................................262
ATmega325P/3250P
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