ATMEGA644PA-PU Atmel, ATMEGA644PA-PU Datasheet - Page 309

• Manufacturer Part Number: ATMEGA644PA-PU
• Description: IC MCU 8BIT 64KB FLASH 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA644PA-PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, TWI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 32
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8272A–AVR–01/10
Figure 26-7. Parallel Programming Timing, Including some General Timing Requirements
Figure 26-8. Parallel Programming Timing, Loading Sequence with Timing Requirements
Note:
Figure 26-9. Parallel Programming Timing, Reading Sequence (within the Same Page) with
Note:
164A/164PA/324A/324PA/644A/644PA/1284/1284P
(DATA, XA0/1, BS1, BS2)
1. The timing requirements shown in
1. The timing requirements shown in
XTAL1
DATA
PAGEL
XTAL1
BS1
XA0
XA1
DATA
OE
apply to loading operation.
apply to reading operation.
BS1
XA0
XA1
Data & Contol
Timing Requirements
RDY/BSY
PAGEL
XTAL1
ADDR0 (Low Byte)
LOAD ADDRESS
ADDR0 (Low Byte)
LOAD ADDRESS
WR
(LOW BYTE)
(LOW BYTE)
t
XLOL
t
OLDV
t
t
BVPH
DVXH
(1)
LOAD DATA
(LOW BYTE)
DATA (Low Byte)
t
t
XHXL
PHPL
(LOW BYTE)
DATA (Low Byte)
Figure 26-7 on page 309
READ DATA
Table 26-7 on page 309
t
t
t
t
t
XLXH
XLDX
XLWL
PLBX
PLWL
t
BVDV
t
(HIGH BYTE)
LOAD DATA
BVWL
DATA (High Byte)
(HIGH BYTE)
READ DATA
DATA (High Byte)
t
XLPH
t
WLWH
LOAD DATA
WLRL
(i.e., t
(i.e., t
t
OHDZ
t
PLXH
DVXH
DVXH
t
WLBX
LOAD ADDRESS
LOAD ADDRESS
, t
(LOW BYTE)
(LOW BYTE)
, t
ADDR1 (Low Byte)
XHXL
ADDR1 (Low Byte)
XHXL
, and t
, and t
t
WLRH
XLDX
XLDX
) also
) also
(1)
309