ATMEGA644-20AU Atmel, ATMEGA644-20AU Datasheet

IC AVR MCU FLASH 64K 44TQFP

ATMEGA644-20AU

Manufacturer Part Number
ATMEGA644-20AU
Description
IC AVR MCU FLASH 64K 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA644-20AU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRZ541, ATAVRRAVEN, ATAVRRZRAVEN, ATAVRRZUSBSTICK, ATAVRRZ201
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
20MHz
Total Internal Ram Size
4KB
# I/os (max)
32
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
TQFP
Package
44TQFP
Family Name
ATmega
Maximum Speed
20 MHz
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Features
Notes:
High-performance, Low-power Atmel
Advanced RISC Architecture
High Endurance Non-volatile Memory segments
JTAG (IEEE std. 1149.1 Compliant) Interface
Peripheral Features
Special Microcontroller Features
I/O and Packages
Speed Grades
Power Consumption at 1 MHz, 3V, 25⋅C
– 131 Powerful Instructions – Most Single-clock Cycle Execution
– 32 × 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
– 64 Kbytes of In-System Self-programmable Flash program memory
– 2 Kbytes EEPROM
– 4 Kbytes Internal SRAM
– Write/Erase cyles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
– Programming Lock for Software Security
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
– Real Time Counter with Separate Oscillator
– Six PWM Channels
– 8-channel, 10-bit ADC
– Byte-oriented Two-wire Serial Interface
– One Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby
– 32 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF
– ATmega644V: 0 - 4 MHz @ 1.8V - 5.5V, 0 - 10 MHz @ 2.7V - 5.5V
– ATmega644: 0 - 10 MHz @ 2.7V - 5.5V, 0 - 20 MHz @ 4.5V - 5.5V
– Active: 240 µA @ 1.8V, 1 MHz
– Power-down Mode: 0.1 µA @ 1.8V
Mode
and Extended Standby
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
Differential mode with selectable gain at 1x, 10x or 200x
1. Worst case temperature. Guaranteed after last write cycle.
2. Failure rate less than 1 ppm.
3. Characterized through accelerated tests.
®
AVR
®
8-bit Microcontroller
(1)(3)
(2)(3)
8-bit
Microcontroller
with 64K Bytes
In-System
Programmable
Flash
ATmega644/V
Preliminary
Summary
2593NS–AVR–07/10

Related parts for ATMEGA644-20AU

ATMEGA644-20AU Summary of contents

Page 1

... Programmable I/O Lines – 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF • Speed Grades – ATmega644V MHz @ 1.8V - 5.5V MHz @ 2.7V - 5.5V – ATmega644 MHz @ 2.7V - 5.5V MHz @ 4.5V - 5.5V • Power Consumption at 1 MHz, 3V, 25⋅C – Active: 240 µA @ 1.8V, 1 MHz – ...

Page 2

... Pin Configurations Figure 1-1. Note: 2593NS–AVR–07/10 Pinout ATmega644 (PCINT8/XCK0/T0) PB0 (PCINT9/CLKO/T1) PB1 (PCINT10/INT2/AIN0) PB2 (PCINT11/OC0A/AIN1) PB3 (PCINT12/OC0B/SS) PB4 (PCINT13/MOSI) PB5 (PCINT14/MISO) PB6 (PCINT15/SCK) PB7 RESET VCC GND XTAL2 XTAL1 (PCINT24/RXD0) PD0 (PCINT25/TXD0) PD1 (PCINT26/INT0) PD2 (PCINT27/INT1) PD3 (PCINT28/OC1B) PD4 ...

Page 3

... AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 2. Overview The ATmega644 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega644 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed ...

Page 4

... Atmel ATmega644 is a powerful microcontroller that provides a highly flexible and cost effec- tive solution to many embedded control applications. The ATmega644 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. ...

Page 5

... As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega644 as listed on 73. 2.2.4 Port B (PB7:PB0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit) ...

Page 6

... AVCC is the supply voltage pin for Port F and the Analog-to-digital Converter. It should be exter- nally connected through a low-pass filter. CC 2.2.11 AREF This is the analog reference pin for the Analog-to-digital Converter. 2593NS–AVR–07/10 , even if the ADC is not used. If the ADC is used, it should be connected CC ATmega644 6 ...

Page 7

... Resources A comprehensive set of development tools, application notes and datasheetsare available for download on http://www.atmel.com/avr. 2593NS–AVR–07/10 ATmega644 7 ...

Page 8

... USART0 I/O Data Register - - - USART0 Baud Rate Register Low Byte - - - UMSEL00 UPM01 UPM00 USBS0 TXCIE0 UDRIE0 RXEN0 TXEN0 TXC0 UDRE0 FE0 DOR0 ATmega644 Bit 2 Bit 1 Bit ...

Page 9

... Timer/Counter1 - Input Capture Register High Byte Timer/Counter1 - Input Capture Register Low Byte Timer/Counter1 - Counter Register High Byte Timer/Counter1 - Counter Register Low Byte - - - FOC1B - - ICES1 - WGM13 WGM12 COM1A0 COM1B1 COM1B0 - - - ADC6D ADC5D ADC4D ADC3D ATmega644 Bit 2 Bit 1 Bit TWAM1 TWAM0 - TWEN - TWIE TWA1 TWA0 TWGCE - TWPS1 TWPS0 ...

Page 10

... Timer/Counter0 Output Compare Register A Timer/Counter0 (8 Bit) FOC0B - - WGM02 COM0A0 COM0B1 COM0B0 - - - - - - EEPROM Address Register Low Byte EEPROM Data Register - EEPM1 EEPM0 EERIE General Purpose I/O Register ATmega644 Bit 2 Bit 1 Bit MUX2 MUX1 MUX0 - ADTS2 ADTS1 ADTS0 ADPS2 ADPS1 ADPS0 - - - - - - - - - - ...

Page 11

... When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O regis- ters as data space using LD and ST instructions, $20 must be added to these addresses. The ATmega644 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions ...

Page 12

... PC ← then PC ← then PC ← then PC ← then PC ← then PC ← ⊕ then PC ← ⊕ then PC ← then PC ← then PC ← then PC ← then PC ← then PC ← ATmega644 Operation Flags #Clocks Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V ...

Page 13

... Y ← (Y) ← ← Rr (Z) ← Rr (Z) ← Rr, Z ← ← (Z) ← ← Rr (k) ← ← (Z) Rd ← (Z) Rd ← (Z), Z ← Z+1 Rd ← (Z) (Z) ← R1:R0 Rd ← P ATmega644 Operation Flags #Clocks None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V ...

Page 14

... Sleep WDR Watchdog Reset BREAK Break 2593NS–AVR–07/10 Description P ← Rr STACK ← ← STACK (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only ATmega644 Operation Flags #Clocks None None None None None None None 1 2 ...

Page 15

... Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 2593NS–AVR–07/10 (2) Ordering Code Package ATmega644V-10AU 44A ATmega644V-10PU 40P6 ATmega644V-10MU 44M1 ATmega644-20AU 44A ATmega644-20PU 40P6 ATmega644-20MU 44M1 318. Package Type ATmega644 (1) Operational Range Industrial ...

Page 16

... Orchard Parkway San Jose, CA 95131 R 2593NS–AVR–07/10 B PIN 1 IDENTIFIER TITLE 44A, 44-lead Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) ATmega644 A2 A COMMON DIMENSIONS (Unit of Measure = mm) MIN SYMBOL NOM A – – A1 0.05 – ...

Page 17

... Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R 2593NS–AVR–07/10 D PIN 0º ~ 15º REF eB TITLE 40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) ATmega644 E1 A1 COMMON DIMENSIONS (Unit of Measure = mm) MIN SYMBOL NOM A – – A1 0.381 – D 52.070 – ...

Page 18

... Pin #1 Chamfer (C 0.30) Option C Pin #1 Notch e (0.20 R) TITLE 44M1, 44-pad 1.0 mm Body, Lead Pitch 0.50 mm, 5.20 mm Exposed Pad, Thermally Enhanced Plastic Very Thin Quad Flat No Lead Package (VQFN) ATmega644 SEATING PLANE SIDE VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A ...

Page 19

... When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does not work from the application code. Problem Fix/Work around Do not set Lock Bit Protection Mode 3 when the application code needs to read from EEPROM. 2593NS–AVR–07/10 ATmega644 . 19 ...

Page 20

... Figure 2-1 on page 3. Updated ”PCIFR – Pin Change Interrupt Flag Register” on page Updated Table 21-4 on page 248. Added note to ”DC Characteristics” on page ATmega644 Table 26-5, “2-wire Serial Bus Require- Table 27-2, “Additional Current Consump- 13. 46. 47. 48. 320. Section 11.1.6 on page 63 page 1 ...

Page 21

... Oscillator Calibration Register” on page Updated Table 26-1 on page 319. Updated typos. Updated ”ADC Noise Reduction Mode” on page Updated ”Power-down Mode” on page Updated ”Calibrated Internal RC Oscillator” on page ATmega644 33. 117. 260. 287. 98, Table 14-3 on page 127, Table 15-3 on page 146, 148. ...

Page 22

... Removed RAMPZ– Extended Z-pointer Register for ELPM/SPM from datasheet. Updated Table 10-1 on page 55. Updated code example in ”Interrupt Vectors in ATmega644” on page Updated ”Setting the Boot Loader Lock Bits by SPM” on page Updated ”Register Summary” on page Removed the occurancy of ATmega164 and ATmega324. ...

Page 23

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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