ATMEGA644-20AU Atmel, ATMEGA644-20AU Datasheet
ATMEGA644-20AU
Specifications of ATMEGA644-20AU
Available stocks
Related parts for ATMEGA644-20AU
ATMEGA644-20AU Summary of contents
Page 1
... Programmable I/O Lines – 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF • Speed Grades – ATmega644V MHz @ 1.8V - 5.5V MHz @ 2.7V - 5.5V – ATmega644 MHz @ 2.7V - 5.5V MHz @ 4.5V - 5.5V • Power Consumption at 1 MHz, 3V, 25⋅C – Active: 240 µA @ 1.8V, 1 MHz – ...
Page 2
... Pin Configurations Figure 1-1. Note: ATmega644 2 Pinout ATmega644 (PCINT8/XCK0/T0) PB0 (PCINT9/CLKO/T1) PB1 (PCINT10/INT2/AIN0) PB2 (PCINT11/OC0A/AIN1) PB3 (PCINT12/OC0B/SS) PB4 (PCINT13/MOSI) PB5 (PCINT14/MISO) PB6 (PCINT15/SCK) PB7 RESET VCC GND XTAL2 XTAL1 (PCINT24/RXD0) PD0 (PCINT25/TXD0) PD1 (PCINT26/INT0) PD2 (PCINT27/INT1) PD3 (PCINT28/OC1B) PD4 (PCINT29/OC1A) PD5 ...
Page 3
... AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 2. Overview The ATmega644 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega644 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed ...
Page 4
... Atmel ATmega644 is a powerful microcontroller that provides a highly flexible and cost effec- tive solution to many embedded control applications. The ATmega644 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. ...
Page 5
... As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega644 as listed on 73. 2.2.4 Port B (PB7:PB0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit) ...
Page 6
... AVCC is the supply voltage pin for Port F and the Analog-to-digital Converter. It should be exter- nally connected through a low-pass filter. CC 2.2.11 AREF This is the analog reference pin for the Analog-to-digital Converter. ATmega644 6 , even if the ADC is not used. If the ADC is used, it should be connected CC 2593N–AVR–07/10 ...
Page 7
... Resources A comprehensive set of development tools, application notes and datasheetsare available for download on http://www.atmel.com/avr. 2593N–AVR–07/10 ATmega644 7 ...
Page 8
... The code examples assume that the part specific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instruc- tions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". ATmega644 8 2593N–AVR–07/10 ...
Page 9
... The program memory is In-System Reprogrammable Flash memory. 2593N–AVR–07/10 Block Diagram of the AVR Architecture Program Flash Counter Program Memory Instruction Register Instruction Decoder Control Lines ATmega644 Data Bus 8-bit Status and Control Interrupt Unit General Purpose SPI Registrers Unit Watchdog ...
Page 10
... The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis- ters, SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega644 has Extended I/O space from 0x100 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used ...
Page 11
... Set Description” for detailed information. • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 2593N–AVR–07/ R/W R/W R/W R ⊕ V ATmega644 R/W R/W R/W R SREG 11 ...
Page 12
... Data Space. Although not being physically imple- mented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. ATmega644 12 shows the structure of the 32 general purpose working registers in the CPU. ...
Page 13
... YH 7 R29 (0x1D R31 (0x1F – – – SP12 SP7 SP6 SP5 SP4 R/W R/W R/W R/W R ATmega644 Figure 5- R26 (0x1A R28 (0x1C R30 (0x1E SP11 SP10 SP9 SP8 SP3 SP2 SP1 SP0 R/W R/W R/W R/W R/W R/W R/W R/W 0 ...
Page 14
... The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in determines the priority levels of the different interrupts. The lower the address the higher is the ATmega644 14 , directly generated from the selected clock source for the ...
Page 15
... EECR |= (1<<EEMPE); /* start EEPROM write */ EECR |= (1<<EEPE); SREG = cSREG; /* restore SREG value (I-bit) */ 2593N–AVR–07/10 ”Memory Programming” on page ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ; restore SREG value (I-bit) ATmega644 ”Interrupts” on page 55 for more information. 284. 15 ...
Page 16
... A return from an interrupt handling routine takes five clock cycles. During these five clock cycles, the Program Counter (three bytes) is popped back from the Stack, the Stack Pointer is incre- mented by three, and the I-bit in SREG is set. ATmega644 16 ; set Global Interrupt Enable 2593N–AVR–07/10 ...
Page 17
... AVR Memories This section describes the different memories in the ATmega644. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega644 features an EEPROM Memory for data storage. All three memory spaces are linear and regular ...
Page 18
... X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O registers, 160 Extended I/O Registers and the 4096 bytes of internal data SRAM in the ATmega644 are all accessible through all these addressing modes. The Register File is described in 12 ...
Page 19
... EEPROM Data Memory The ATmega644 contains 2 Kbytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...
Page 20
... I/O Memory The I/O space definition of the ATmega644 is shown in All ATmega644 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...
Page 21
... Initial Value • Bits 15:12 – Res: Reserved Bits These bits are reserved bits in the ATmega644 and will always read as zero. • Bits 11:0 – EEAR8:0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 4 Kbytes EEPROM space ...
Page 22
... When the write access time has elapsed, the EEPE bit is cleared by hardware. The user soft- ware can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed. ATmega644 22 EEPROM Mode Bits ...
Page 23
... Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish. 2593N–AVR–07/10 EEPROM Programming Time Number of Calibrated RC Oscillator Cycles 26,368 ATmega644 Table 6-2 lists the typical pro- Typ Programming Time 3 ...
Page 24
... Wait for completion of previous write */ while(EECR & (1<<EEPE)) /* Set up address and Data Registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMPE */ EECR |= (1<<EEMPE); /* Start eeprom write by setting EEPE */ EECR |= (1<<EEPE); } Note: ATmega644 24 (1) ( See “About Code Examples” on page 8. 2593N–AVR–07/10 ...
Page 25
... Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from Data Register */ return EEDR; 1. See “About Code Examples” on page MSB R/W R/W R MSB R/W R/W R ATmega644 R/W R/W R/W R R/W R/W R/W R LSB GPIOR2 ...
Page 26
... GPIOR0 – General Purpose I/O Register 0 Bit 0x1E (0x3E) Read/Write Initial Value Note: ATmega644 MSB R/W R/W R SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector). The ALE pulse in period T4 is only present if the next instruction accesses the RAM (internal or external) ...
Page 27
... ASY Source clock System Clock Prescaler Clock Multiplexer Timer/Counter External Clock Oscillator Oscillator is halted, TWI address recognition in all sleep modes. I/O ATmega644 Flash and CPU Core RAM EEPROM ADC clk CPU clk FLASH Reset Logic Watchdog Timer Watchdog clock Watchdog ...
Page 28
... To ensure sufficient V the device reset is released by all other reset sources. describes the start conditions for the internal reset. The delay (t Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The ATmega644 28 ASY Device Clocking Options Select 1. For all fuses “ ...
Page 29
... Table 7-2. The frequency of the Watchdog Oscillator is voltage ”Typical Characteristics” on page Number of Watchdog Oscillator Cycles = 5.0V) Typ Time-out ( 4 Crystal Oscillator Connections C2 C1 ATmega644 326. = 3.0V) Number of Cycles 4.3 ms 512 (8,192) Figure 7-2. Either a quartz crys- XTAL2 XTAL1 ...
Page 30
... Power Conditions Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Ceramic resonator, BOD enabled Ceramic resonator, fast rising power Ceramic resonator, slowly rising power ATmega644 30 31. Low Power Crystal Oscillator Operating Modes (1) (MHz) CKSEL3..1 0.4 - 0.9 100 0.9 - 3.0 101 3 ...
Page 31
... Start-up Times for the Full Swing Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save 258 CK 258 ATmega644 Additional Delay from Reset (V = 5.0V) CKSEL0 CC 14CK 14CK + 4.1 ms 14CK + 65 ms 30. Note that the Full Swing Crystal ” ...
Page 32
... Table 7-7. Power Conditions BOD enabled Fast rising power Slowly rising power BOD enabled Fast rising power Slowly rising power Note: ATmega644 32 Start-up Times for the Full Swing Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save 1K CK 16K CK 16K CK 16K CK 1 ...
Page 33
... Start-up times for the internal calibrated RC Oscillator clock selection Start-up Time from Power- down and Power-save Reserved The device is shipped with this option selected. 1. ATmega644 for more details. The device is shipped for more details. ”OSCCAL – Oscillator Calibration Register” on Table 26-1 on page 287. (1)(3) CKSEL3..0 0010 ...
Page 34
... Table 7-11. Table 7-11. Power Conditions BOD enabled Fast rising power Slowly rising power ATmega644 34 128 kHz Internal Oscillator Operating Modes Nominal Frequency 128 kHz 1. The frequency is preliminary value. Actual value is TBD. Start-up Times for the 128 kHz Internal Oscillator Start-up Time from Power- ...
Page 35
... EXTERNAL CLOCK SIGNAL Crystal Oscillator Clock Frequency Nominal Frequency MHz Start-up Times for the External Clock Selection Start-up Time from Power- down and Power-save Reserved ATmega644 XTAL2 XTAL1 GND CKSEL3..0 0000 Additional Delay from Reset (V = 5.0V) SUT1..0 CC 14CK 14CK + 4.1 ms 14CK + 65 ms ” ...
Page 36
... System Clock Prescaler The ATmega644 has a system clock prescaler, and the system clock can be divided by setting the ”CLKPR – Clock Prescale Register” on page system clock frequency and the power consumption when the requirement for processing power is low ...
Page 37
... R/W R/W R/W R/W Device Specific Calibration Value Table 26-1 on page 319. The application software can write this register to change 319. Calibration outside that range is not guaranteed CLKPCE – – R ATmega644 CAL3 CAL2 CAL1 R/W R/W R – CLKPS3 CLKPS2 CLKPS1 R R/W ...
Page 38
... Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. Table 7-14. CLKPS3 ATmega644 38 Clock Prescaler Select CLKPS2 CLKPS1 ...
Page 39
... SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. 2593N–AVR–07/10 presents the different clock systems in the ATmega644, and their distri- Oscillators (2) X ...
Page 40
... This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the Reset Time-out period, as described in ATmega644 40 and clk , while allowing the other clocks to run. ...
Page 41
... In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption. 2593N–AVR–07/10 44, provides a method to stop the clock to indi- ”Supply Current of IO modules” on page 331 ATmega644 for examples. In all other 41 ...
Page 42
... V For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to V input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and ATmega644 42 ”Analog Comparator” on page 230 for details on the start-up time. ...
Page 43
... Sleep Mode Select SM1 SM0 Standby modes are only recommended for use with external crystals or resonators. ATmega644 and – SM2 SM1 SM0 R R/W R/W R Table 8-2. Sleep Mode Idle ADC Noise Reduction Power-down Power-save Reserved Reserved (1) Standby (1) Extended Standby ”DIDR0 – Digital ...
Page 44
... When waking up the USART0 again, the USART0 should be reinitialized to ensure proper operation. • Bit 0 - PRADC: Power Reduction ADC Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down. ATmega644 ...
Page 45
... Reset Sources The ATmega644 has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. • ...
Page 46
... A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V when V CC Figure 9-2. TIME-OUT INTERNAL ATmega644 46 Reset Logic Power-on Reset Circuit Brown-out Reset Circuit Pull-up Resistor ...
Page 47
... Figure 9-4. 9.2.3 Brown-out Detection ATmega644 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V ing operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V ...
Page 48
... Timer” on page 49 Figure 9-6. 9.3 Internal Voltage Reference ATmega644 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 9.3.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in reference is not always turned on ...
Page 49
... Watchdog Timer ATmega644 has an Enhanced Watchdog Timer (WDT). The main features are: • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from • Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode Figure 9-7 ...
Page 50
... Write logical one to WDCE and WDE */ /* Keep old prescaler setting to prevent unintentional time-out */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCSR = 0x00; __enable_interrupt(); } Note: ATmega644 50 (1) r16, MCUSR r16, (0xff & (0<<WDRF)) MCUSR, r16 r16, WDTCSR r16, (1<<WDCE) | (1<<WDE) WDTCSR, r16 r16, (0< ...
Page 51
... Turn on global interrupt sei ret (1) __disable_interrupt(); __watchdog_reset(); /* Start timed equence */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Set new prescaler(time-out) value = 64K cycles (~0 WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0); __enable_interrupt(); 1. The example code assumes that the part specific header file is included. ATmega644 51 ...
Page 52
... Bit 6 - WDIE: Watchdog Interrupt Enable When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs. ATmega644 ...
Page 53
... ATmega644 Action on Time-out None Interrupt Reset Interrupt, then go to System Reset Mode Reset Typical Time-out at Cycles (2048) cycles 4K (4096) cycles 8K (8192) cycles = 5. 0.125s 0.25s 0.5s 1.0s 2 ...
Page 54
... Table 9-2. WDP3 ATmega644 54 Watchdog Timer Prescale Select Number of WDT Oscillator WDP2 WDP1 WDP0 512K (524288) cycles 1024K (1048576) cycles Typical Time-out at Cycles V = 5.0V CC 4.0s 8.0s Reserved 2593N–AVR–07/10 ...
Page 55
... Interrupts This section describes the specifics of the interrupt handling as performed in ATmega644. For a general explanation of the AVR interrupt handling, refer to page 14. 10.1 Interrupt Vectors in ATmega644 Table 10-1. Vector No 2593N–AVR–07/10 Reset and Interrupt Vectors Program (2) Address Source (1) $0000 RESET $0002 INT0 ...
Page 56
... Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 10-2. BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega644 is: Address 0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E ...
Page 57
... SPM_RDY ; SPM Ready Handler r16,high(RAMEND); Main program start out SPH,r16 ; Set Stack Pointer to top of RAM ATmega644 ; ADC Conversion Complete Handler ; EEPROM Ready Handler ; 2-wire Serial Handler ; SPM Ready Handler ; Main program start ; Set Stack Pointer to top of RAM ; Enable interrupts ...
Page 58
... Within four cycles, write the desired value to IVSEL while writing a zero to IVCE. Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to ATmega644 58 ldi r16,low(RAMEND) ...
Page 59
... MCUCR, r16 ; Move interrupts to Boot Flash section ldi r17, (1<<IVSEL) out MCUCR, r17 ret /* Get MCUCR*/ temp = MCUCR /* Enable change of Interrupt Vectors */ MCUCR = temp|(1<<IVCE); /* Move interrupts to Boot Flash section */ MCUCR = temp|(1<<IVSEL); ATmega644 ”Memory Programming” on page 284 59 ...
Page 60
... Initial Value • Bits 7:6 – Reserved These bits are reserved in the ATmega644, and will always read as zero. • Bits 5:0 – ISC21, ISC20 – ISC00, ISC00: External Interrupt Sense Control Bits The External Interrupts are activated by the external pins INT2:0 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set ...
Page 61
... Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed. Asynchronous External Interrupt Characteristics Parameter Minimum pulse width for asynchronous external interrupt – – – – – – R for more information. ATmega644 Condition Min Typ – – INT2 INT1 R R R/W R – – INTF2 INTF1 R ...
Page 62
... When a logic change on any PCINT23:16 pin triggers an interrupt request, PCIF2 becomes set (one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter- natively, the flag can be cleared by writing a logical one to it. ATmega644 ...
Page 63
... PCINT30 PCINT29 PCINT28 R/W R/W R/W R PCINT23 PCINT22 PCINT21 PCINT20 R/W R/W R/W R PCINT15 PCINT14 PCINT13 PCINT12 R/W R/W R/W R ATmega644 PCINT27 PCINT26 PCINT25 PCINT24 R/W R/W R/W R PCINT19 PCINT18 PCINT17 PCINT16 R/W R/W R/W R PCINT11 PCINT10 PCINT9 PCINT8 R/W R/W ...
Page 64
... Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7:0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the cor- responding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. ATmega644 ...
Page 65
... Ground as indicated in CC for a complete list of parameters. Pxn C pin ”Register Description” on page 71. Refer to the individual module sections for a full description of the alter- ATmega644 Figure 12-1. Refer to ”Electrical Char Logic See Figure "General Digital I/O" for Details 84. ” ...
Page 66
... If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running. ATmega644 66 (1) Pxn ...
Page 67
... Input 1 1 Input 0 X Output 1 X Output Figure 12-2, the PINxn Register bit and the preceding latch con- pd,max ATmega644 Pull-up Comment No Tri-state (Hi-Z) Yes Pxn will source current if ext. pulled low. No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) Figure 12-3 ...
Page 68
... The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. ATmega644 68 SYSTEM CLK XXX ...
Page 69
... Figure 12-2, the digital input signal can be clamped to ground at the input of the ”Alternate Port Functions” on page ATmega644 /2. CC 71. 69 ...
Page 70
... In this case, the pull-up will be disabled during reset. If low power consumption during reset is important recommended to use an external pull-up or pull-down. Connecting unused pins directly to V accidentally configured as an output. ATmega644 70 or GND is not recommended, since this may cause excessive currents if the pin is CC ...
Page 71
... Pxn, PORT TOGGLE OVERRIDE ENABLE 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. All other signals are unique for each pin. ATmega644 Figure 12-2 can be overridden by ...
Page 72
... The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. ATmega644 72 summarizes the function of the overriding signals. The pin and port indexes from are not shown in the succeeding tables. The overriding signals are generated internally ...
Page 73
... ADC4 (ADC input channel 4) PCINT4 (Pin Change Interrupt 4) ADC3 (ADC input channel 3) PCINT3 (Pin Change Interrupt 3) ADC2 (ADC input channel 2) PCINT2 (Pin Change Interrupt 2) ADC1 (ADC input channel 1) PCINT1 (Pin Change Interrupt 1) ADC0 (ADC input channel 0) PCINT0 (Pin Change Interrupt 0) ATmega644 . 73 ...
Page 74
... DIEOV DI AIO Table 12-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATmega644 74 and Table 12-5 relates the alternate functions of Port A to the overriding signals Figure 12-5 on page 71. Overriding Signals for Alternate Functions in PA7:PA4 PA7/ADC7/ PA6/ADC6/ PCINT7 PCINT6 ...
Page 75
... AIN0 (Analog Comparator Positive Input) INT2 (External Interrupt 2 Input) PCINT10 (Pin Change Interrupt 10) T1 (Timer/Counter 1 External Counter Input) CLKO (Divided System Clock Output) PCINT9 (Pin Change Interrupt 9) T0 (Timer/Counter 0 External Counter Input) XCK0 (USART0 External Clock Input/Output) PCINT8 (Pin Change Interrupt 8) ATmega644 Table 12-6. 75 ...
Page 76
... CLKO, Divided System Clock: The divided system clock can be output on the PB1 pin. The divided system clock will be output if the CKOUT Fuse is programmed, regardless of the PORTB1 and DDB1 settings. It will also be output during reset. PCINT9, Pin Change Interrupt source 9: The PB1 pin can serve as an external interrupt source. ATmega644 76 2593N–AVR–07/10 ...
Page 77
... OC0B 0 INT2 ENABLE PCINT11 • PCIE1 PCINT10 • PCIE1 1 1 INT2 INPUT PCINT11 INPUT PCINT10 INPUT – – ATmega644 PB5/MOSI/ PB4/SS/OC0B/ PCINT13 PCINT12 SPE • MSTR SPE • MSTR PORTB13 • PUD PORTB12 • PUD SPE • MSTR SPE • MSTR 0 0 SPE • ...
Page 78
... TDO/PCINT20 – Port C, Bit 4 TDO, JTAG Test Data Output. PCINT20, Pin Change Interrupt source 20: The PC4 pin can serve as an external interrupt source. ATmega644 78 Port C Pins Alternate Functions Alternate Function TOSC2 (Timer Oscillator pin 2) PCINT23 (Pin Change Interrupt 23) ...
Page 79
... AS2 • EXCLK AS2 0 0 AS2 • EXCLK AS2 AS2 • EXCLK + AS2 PCINT23 • PCIE2 0 EXCLK PCINT23 INPUT PCINT22 INPUT T/C2 OSC T/C2 OSC OUTPUT INPUT ATmega644 PC5/TDI/ PC4/TDO/ PCINT21 PCINT20 JTAGEN JTAGEN 1 0 JTAGEN JTAGEN SHIFT_IR + 0 SHIFT_DR 0 JTAGEN 0 TDO JTAGEN JTAGEN 0 0 ...
Page 80
... DIEOE DIEOV DI AIO 12.3.4 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 12-12. Port D Pins Alternate Functions Port Pin PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 ATmega644 80 PC3/TMS/ PC2/TCK/ PCINT19 PCINT18 JTAGEN JTAGEN 1 1 JTAGEN JTAGEN ...
Page 81
... PCINT28, Pin Change Interrupt Source 28: The PD4 pin can serve as an external interrupt source. • INT1/PCINT27 – Port D, Bit 3 INT1, External Interrupt source 1. The PD3 pin can serve as an external interrupt source to the MCU. PCINT27, Pin Change Interrupt Source 27: The PD3 pin can serve as an external interrupt source. 2593N–AVR–07/10 ATmega644 81 ...
Page 82
... Table 12-13. Overriding Signals for Alternate Functions PD7:PD4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATmega644 82 and Table 12-14 relates the alternate functions of Port D to the overriding signals Figure 12-5 on page 71. PD6/ICP1/ PD7/OC2A/ OC2B/ PCINT31 PCINT30 0 ...
Page 83
... When enabled, the 2-wire Serial Interface enables Slew-Rate controls on the output pins PD0 and PD1. This is not shown in this table. In addition, spike filters are connected between the AIO outputs shown in the port figure and the digital logic of the TWI module. ATmega644 (1) PD1/TXD0/ ...
Page 84
... PORTB – Port B Data Register Bit 0x05 (0x25) Read/Write Initial Value 12.3.10 DDRB – Port B Data Direction Register Bit 0x04 (0x24) Read/Write Initial Value 12.3.11 PINB – Port B Input Pins Address Bit 0x03 (0x23) Read/Write Initial Value ATmega644 JTD – – PUD R R for more details about this feature ...
Page 85
... R/W R/W R/W R DDD7 DDD6 DDD5 DDD4 R/W R/W R/W R PIND7 PIND6 PIND5 PIND4 R/W R/W R/W R/W N/A N/A N/A N/A ATmega644 PORTC3 PORTC2 PORTC1 PORTC0 R/W R/W R/W R DDC3 DDC2 DDC1 DDC0 R/W R/W R/W R PINC3 PINC2 PINC1 PINC0 ...
Page 86
... Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler external clock source on the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter ATmega644 86 ”Pinout ATmega644” on page ”Register Description” on page 97. Count Clear ...
Page 87
... The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The assignment is depen- dent on the mode of operation. ”Timer/Counter Prescaler” on page DATA BUS count clear TCNTn direction bottom ATmega644 145. TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ...
Page 88
... WGM02:0 bits and Compare Output mode (COM0x1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation Figure 13-3 ATmega644 88 Increment or decrement TCNT0 by 1. Select between increment and decrement. ...
Page 89
... Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the Compare Match will be missed, resulting in incorrect waveform 2593N–AVR–07/10 DATA BUS OCRnx = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 ATmega644 TCNTn OCFnx (Int.Req.) OCnx COMnX1:0 89 ...
Page 90
... The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC0x state before the out- put is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of operation. ATmega644 90 COMnx1 Waveform ...
Page 91
... Compare Match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. 2593N–AVR–07/10 Table 13-2 on page 97. For fast PWM mode, refer to Table 13-4 on page 115.). ”Timer/Counter Timing Diagrams” on page Figure 13-5. The counter value (TCNT0) ATmega644 Table 13-3 on 98. 95. 91 ...
Page 92
... In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast ATmega644 92 1 ...
Page 93
... The TCNT0 value is in the timing diagram shown as a his Table 13-3 on page 97). The actual OC0x value will only be visible on the ----------------- - OCnxPWM N 256 = f OC0 ATmega644 OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set (COMnx1 (COMnx1 clk_I/O ⋅ /2 when OCR0A is set to zero. This clk_I/O 93 ...
Page 94
... In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to ATmega644 94 13-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating ...
Page 95
... Figure 13-8 contains timing data for basic Timer/Counter operation. The figure I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. ATmega644 98). The actual OC0x value will only be f clk_I/O = ----------------- - ⋅ N 510 OCnx has a transition from high to low even though Figure 13-7 ...
Page 96
... PWM mode where OCR0A is TOP. Figure 13-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- clk clk (clk I/O TCNTn (CTC) OCRnx OCFnx ATmega644 96 I/O Tn /8) MAX - 1 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC I/O Tn /8) ...
Page 97
... Set OC0A on Compare Match, clear OC0A at BOTTOM 1 (inverting mode special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done at BOTTOM. See page 92 for more details. ATmega644 COM0B0 – – ...
Page 98
... Table 13-3 mode. Table 13-6. COM01 ATmega644 98 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase cor- Compare Output Mode, Phase Correct PWM Mode COM0A0 Description 0 Normal port operation, OC0A disconnected. WGM02 = 0: Normal Port Operation, OC0A Disconnected. 1 WGM02 = 1: Toggle OC0A on Compare Match ...
Page 99
... Note: • Bits 3:2 – Res: Reserved Bits These bits are reserved bits in the ATmega644 and will always read as zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting ...
Page 100
... These bits are reserved bits and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the • Bits 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 13-9. CS02 ATmega644 100 FOC0A FOC0B – ...
Page 101
... External clock source on T0 pin. Clock on falling edge External clock source on T0 pin. Clock on rising edge R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R – – – – ATmega644 TCNT0[7:0] R/W R/W R OCR0A[7:0] R/W R/W R OCR0B[7:0] R/W R/W R – OCIE0B OCIE0A R R/W R ...
Page 102
... Initial Value • Bits 7:3 – Res: Reserved Bits These bits are reserved bits in the ATmega644 and will always read as zero. • Bit 2 – OCF0B: Timer/Counter 0 Output Compare B Match Flag The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B – ...
Page 103
... The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Generation Mode Bit Description” on page 2593N–AVR–07/10 ATmega644 Table 99. 13-8, ”Waveform 103 ...
Page 104
... I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca- tions are listed in the The PRTIM1 bit in enable Timer/Counter1 module. ATmega644 104 ”Pinout ATmega644” on page ”Register Description” on page 125. ”PRR – Power Reduction Register” on page 44 Figure 14-1. For the actual 2 ...
Page 105
... Count Clear Control Logic Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA Refer to Figure 1-1 on page 2 and ”Alternate Port Functions” on page 71 placement and description. ATmega644 (Note:) TOVn (Int.Req.) Clock Select clk Tn Edge Detector TOP BOTTOM ( From Prescaler ) = = 0 OCnA (Int.Req.) Waveform ...
Page 106
... The same principle can be used directly for accessing the OCRnA/B/C and ICRn Registers. Note that when using “C”, the compiler handles the 16-bit access. ATmega644 106 113.. The compare match event will also set the Compare Match 230 ...
Page 107
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATmega644 107 ...
Page 108
... SREG = sreg; return i; } Note: The assembly code example returns the TCNTn value in the r17:r16 register pair. ATmega644 108 (1) (1) 1. The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” ...
Page 109
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ”Timer/Counter Prescaler” on page ATmega644 145. 109 ...
Page 110
... There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OCnx. For more details about advanced counting sequences and waveform generation, see ATmega644 110 shows a block diagram of the counter and its surroundings. ...
Page 111
... ICRn Register for defining the counter’s TOP value. In these cases the Waveform Genera- 2593N–AVR–07/10 DATA BUS TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) ICRn (16-bit Register) WRITE ACO* ACIC* Analog Comparator ICPn ATmega644 Figure 14-3. The elements of (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Edge ICFn (Int.Req.) Canceler ...
Page 112
... Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICRn Register has been read. After a change of the edge, the Input Capture Flag (ICFn) must be ATmega644 112 106. ...
Page 113
... Output Compare unit. The small “n” in the register and DATA BUS TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) TOP BOTTOM ATmega644 116.) (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) = (16-bit Comparator ) OCFnx (Int.Req.) Waveform Generator WGMn3:0 ...
Page 114
... Normal mode. The OCnx Register keeps its value even when changing between Waveform Generation modes. Be aware that the COMnx1:0 bits are not double buffered together with the compare value. Changing the COMnx1:0 bits will take effect immediately. ATmega644 114 106. ”Accessing 16-bit Registers” ...
Page 115
... The design of the Output Compare pin logic allows initialization of the OCnx state before the out- put is enabled. Note that some COMnx1:0 bit settings are reserved for certain modes of operation. The COMnx1:0 bits have no effect on the Input Capture unit. 2593N–AVR–07/10 Waveform Generator I/O See Section “14.11” on page 125. ATmega644 Figure 14 OCnx ...
Page 116
... The OCRnA or ICRn define the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the opera- tion of counting external events. ATmega644 116 Table 14-2 on page 125. For fast PWM mode refer to 115.) ” ...
Page 117
... PWM mode can be twice as high as the phase cor- 2593N–AVR–07/ when OCRnA is set to zero (0x0000). The waveform frequency clk_I -------------------------------------------------- - OCnA ⋅ ATmega644 Figure 14-6. The counter value (TCNTn) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnA1 clk_I/O ⋅ OCRnA 1 + 117 ...
Page 118
... Note that when using fixed TOP values the unused bits are masked to zero when any of the OCRnx Registers are written. The procedure for updating ICRn differs from updating OCRnA when used for defining the TOP value. The ICRn Register is not double buffered. This means that if ICRn is changed to a low ATmega644 118 ( TOP ...
Page 119
... In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope 2593N–AVR–07/10 Table on page f clk_I ---------------------------------- - OCnxPWM ⋅ TOP when OCRnA is set to zero (0x0000). This feature clk_I/O ATmega644 126). The actual OCnx ) 119 ...
Page 120
... Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNTn and the OCRnx. Note that when using fixed TOP values, the unused bits are masked to zero when any of the ATmega644 120 ( ...
Page 121
... Figure The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and 2593N–AVR–07/10 f OCnxPCPWM 14-9). ATmega644 Figure 14-8 illustrates, changing the Table on page f clk_I/O = --------------------------- - ⋅ ...
Page 122
... Compare Registers, a compare match will never occur between the TCNTn and the OCRnx. As Figure 14-9 cal in all periods. Since the OCRnx Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore frequency correct. ATmega644 122 log R = ---------------------------------- - ...
Page 123
... OCnxPFCPWM Figure 14-10 clk I/O clk Tn (clk /1) I/O TCNTn OCRnx - 1 OCRnx OCFnx shows the same timing data, but with the prescaler enabled. ATmega644 f clk_I/O = --------------------------- - ⋅ ⋅ TOP ) is therefore shown shows a timing diagram for the setting of OCFnx. OCRnx OCRnx + 1 OCRnx Value Table on ...
Page 124
... TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOVn Flag at BOTTOM. Figure 14-12. Timer/Counter Timing Diagram, no Prescaling (CTC and FPWM) (PC and PFC PWM) TOVn and ICFn (Update at TOP) Figure 14-13 ATmega644 124 clk I/O clk Tn /8) I/O OCRnx - 1 OCRnx shows the count sequence close to TOP in various modes ...
Page 125
... OCRnx Old OCRnx Value (Update at TOP COM1A1 COM1A0 COM1B1 R/W R/W R Table 14-2 Compare Output Mode, non-PWM COMnA0/COMnB0 ATmega644 /8) clk_I/O TOP BOTTOM TOP TOP - 1 New OCRnx Value COM1B0 – – WGM11 R R shows the COMnx1:0 bit functionality when the Description Normal port operation, OCnA/OCnB disconnected. ...
Page 126
... Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. ATmega644 126 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast Compare Output Mode, Fast PWM ...
Page 127
... CTC 0 1 (Reserved Fast PWM 1 1 Fast PWM ICNC1 ICES1 – WGM13 R/W R ATmega644 Update of x TOP OCRn 0xFFFF Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP OCRnA Immediate 0x00FF BOTTOM 0x01FF BOTTOM 0x03FF BOTTOM ICRn BOTTOM OCRnA BOTTOM ICRn ...
Page 128
... FOCnA/FOCnB bit, an immediate compare match is forced on the Waveform Generation unit. The OCnA/OCnB output is changed according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB bits are implemented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the effect of the forced compare. ATmega644 128 Figure 14-11. ...
Page 129
... TCNT1[15:8] TCNT1[7:0] R/W R/W R/W R OCR1A[15:8] OCR1A[7:0] R/W R/W R/W R OCR1B[15:8] OCR1B[7:0] R/W R/W R/W R See Section “14.3” on page 106. ATmega644 R/W R/W R/W R See Section “14.3” R/W R/W R/W R R/W R/W R/W R TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ...
Page 130
... Initial Value • Bit 7:6 – Res: Reserved Bits These bits are unused bits in the ATmega644, and will always read as zero. • Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (see “ ...
Page 131
... Initial Value • Bit 7:6 – Res: Reserved Bits These bits are unused bits in the ATmega644, and will always read as zero. • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGMn3 used as the TOP value, the ICF1 Flag is set when the coun- ter reaches the TOP value ...
Page 132
... I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the The Power Reduction Timer/Counter2 bit, PRTIM2, in page 44 Figure 15-1. 8-bit Timer/Counter Block Diagram ATmega644 132 ”Pin Configurations” on page ”Register Description” on page must be written to zero to enable Timer/Counter2 module. ...
Page 133
... OCR2A Register. The assignment is depen- dent on the mode of operation default equal to the MCU clock, clk T2 145. ATmega644 for details. The compare match event will also set the 150. For details on clock sources and prescaler, see . When the AS2 I/O ” ...
Page 134
... WGM22:0 bits and Compare Output mode (COM2x1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation Figure 14-10 on page 123 ATmega644 134 DATA BUS count ...
Page 135
... OCR2x value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting. 2593N–AVR–07/10 DATA BUS OCRnx = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 ATmega644 TCNTn OCFnx (Int.Req.) OCnx COMnX1:0 135 ...
Page 136
... The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC2x state before the out- put is enabled. Note that some COM2x1:0 bit settings are reserved for certain modes of operation. ATmega644 136 Waveform D ...
Page 137
... TCNT2 and OCR2A, and then counter (TCNT2) is cleared. 2593N–AVR–07/10 Table 15-5 on page 147. For fast PWM mode, refer to Table 15-7 on page 136.). ”Timer/Counter Timing Diagrams” on page Table ATmega644 Table 15-6 on 148. 141. 15-5. The counter value (TCNT2) 137 ...
Page 138
... PWM mode can be twice as high as the phase correct PWM mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. ATmega644 138 1 2 ...
Page 139
... Figure 15-6 on page 139. The TCNT2 value is in the timing diagram Table 15-3 on page f clk_I ----------------- - OCnxPWM N 256 ATmega644 OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set (COMnx1 (COMnx1 146). The actual OC2x value will only ⋅ 139 ...
Page 140
... In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM ATmega644 140 15-7. The TCNT2 value is in the timing diagram shown as a histogram for illustrating ...
Page 141
... OCnxPCPWM Figure 15-7 contains timing data for basic Timer/Counter operation. The figure shows the I/O Tn /1) I/O MAX - 1 ATmega644 Table 15-4 on page 147). The actual OC2x f clk_I/O = ----------------- - ⋅ N 510 OCnx has a transition from high to low even though Figure 15-7 ...
Page 142
... Figure 15-10 Figure 15-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f clk clk (clk TCNTn OCRnx OCFnx Figure 15-11 ATmega644 142 shows the same timing data, but with the prescaler enabled. I/O Tn /8) I/O MAX - 1 MAX shows the setting of OCF2A in all modes except CTC mode. ...
Page 143
... The interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up and re- 2593N–AVR–07/10 caler (f /8) clk_I/O clk I/O clk Tn /8) I/O TOP - 1 Enable interrupts, if needed. ATmega644 TOP BOTTOM BOTTOM + 1 TOP 143 ...
Page 144
... The timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the Interrupt Flag. The Output Compare pin is changed on the timer clock and is not synchronized to the processor clock. ATmega644 144 2593N–AVR–07/10 ...
Page 145
... TOSC1 AS2 PSRASY CS20 CS21 CS22 . By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously IO /256, and clk /1024. Additionally, clk T2S T2S ATmega644 10-BIT T/C PRESCALER 0 TIMER/COUNTER2 CLOCK SOURCE clk T2 . clk is by default connected to the main T2S T2S for details. /8, clk T2S T2S as well as 0 (stop) may be selected ...
Page 146
... WGM22:0 bit setting. are set to a normal or CTC mode (non-PWM). Table 15-2. COM2A1 Table 15-3 mode. Table 15-3. COM2A1 Note: ATmega644 146 COM2A1 COM2A0 COM2B1 COM2B0 R/W R/W R Table 15-2 shows the COM2A1:0 bit functionality when the WGM22:0 bits Compare Output Mode, non-PWM Mode ...
Page 147
... COM2B1:0 bit functionality when the WGM22:0 bits are set to fast PWM Compare Output Mode, Fast PWM Mode COM2B0 Description 0 Normal port operation, OC2B disconnected. 1 Reserved Clear OC2B on Compare Match, set OC2B at BOTTOM 0 (non-inverting mode) Set OC2B on Compare Match, clear OC2B at BOTTOM 1 (inverting mode) ATmega644 (1) ”Phase Correct PWM Mode” on (1) 147 ...
Page 148
... Note: • Bits 3:2 – Res: Reserved Bits These bits are reserved bits in the ATmega644 and will always read as zero. • Bits 1:0 – WGM21:0: Waveform Generation Mode Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting ...
Page 149
... OCR2B as TOP. The FOC2B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the ATmega644 and will always read as zero. • Bit 3 – WGM22: Waveform Generation Mode See the description in the • Bit 2:0 – CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see 15-9 ...
Page 150
... The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt generate a waveform output on the OC2B pin. 15.11.6 ASSR – Asynchronous Status Register Bit (0xB6) Read/Write Initial Value ATmega644 150 Clock Select Bit Description CS21 CS20 Description 1 1 clk ...
Page 151
... The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are different. When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B, TCCR2A and TCCR2B the value in the temporary storage register is read. 2593N–AVR–07/10 ATmega644 . When AS2 is I/O 151 ...
Page 152
... Bit 0 – TOV2: Timer/Counter2 Overflow Flag The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hard- ware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Inter- ATmega644 152 7 6 ...
Page 153
... Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. 2593N–AVR–07/ TSM – – – R ATmega644 – – PSRASY PSRSYNC GTCCR R R R/W R 153 ...
Page 154
... Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega644 and peripheral devices or between several AVR devices. USART can also be used in Master SPI mode, see “USART in SPI Mode” on page 191. The Power Reduction SPI bit, PRSPI must be written to zero to enable SPI module ...
Page 155
... In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high periods should be: Low period: longer than 2 CPU clock cycles. High period: longer than 2 CPU clock cycles. 2593N–AVR–07/10 ATmega644 Figure 16-2. The sys- SHIFT ENABLE ...
Page 156
... Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. For example, if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB. ATmega644 156 Table 16-1. For more details on automatic port overrides, refer to 71 ...
Page 157
... Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; 1. See “About Code Examples” on page 8. ATmega644 157 ...
Page 158
... Enable SPI */ SPCR = (1<<SPE); } char SPI_SlaveReceive(void Wait for reception complete */ while(!(SPSR & (1<<SPIF))) /* Return Data Register */ return SPDR; } Note: ATmega644 158 (1) r17,(1<<DD_MISO) DDR_SPI,r17 r17,(1<<SPE) SPCR,r17 r16,SPDR ( See “About Code Examples” on page 8. 2593N–AVR–07/10 ...
Page 159
... This is clearly seen by summarizing Table 16-3 2593N–AVR–07/10 Figure 16-4. Data bits are shifted out and latched in on opposite edges of the SCK sig- and Table 16-4, as done below: ATmega644 Figure 159 ...
Page 160
... Table 16-2. CPOL=0, CPHA=0 CPOL=0, CPHA=1 CPOL=1, CPHA=0 CPOL=1, CPHA=1 Figure 16-3. SPI Transfer Format with CPHA = 0 Figure 16-4. SPI Transfer Format with CPHA = 1 ATmega644 160 CPOL Functionality Leading Edge Sample (Rising) Setup (Rising) Sample (Falling) Setup (Falling) SCK (CPOL = 0) mode 0 ...
Page 161
... Figure 16-3 and Figure 16-4 CPOL Functionality CPOL Leading Edge 0 Rising 1 Falling Figure 16-3 CPHA Functionality CPHA Leading Edge 0 Sample 1 Setup ATmega644 CPOL CPHA SPR1 SPR0 R/W R/W R/W R for an example. The CPOL functionality is sum- Trailing Edge Falling Rising and Figure 16-4 for an example ...
Page 162
... When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work lower. The SPI interface on the ATmega644 is also used for program memory and EEPROM down- loading or uploading. See ATmega644 162 ...
Page 163
... The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis- ter causes the Shift Register Receive buffer to be read. 2593N–AVR–07/ MSB R/W R/W R/W R ATmega644 LSB R/W R/W R/W R SPDR Undefined 163 ...
Page 164
... Multi-processor Communication Mode • Double Speed Asynchronous Communication Mode The ATmega644 has one USART, USART0. The functionality is described below, most register and bit references in this section are written in general form. A lower case “n” replaces the USART number. 17.2 Overview The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device ...
Page 165
... UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA 1. See Figure 1-1 on page 2 and ”Alternate Port Functions” on page 71 placement. ATmega644 Clock Generator OSC SYNC LOGIC PIN XCK CONTROL Transmitter TX CONTROL PARITY GENERATOR PIN TxD ...
Page 166
... UMSELn, U2Xn and DDR_XCKn bits. Table 17-1 ing the UBRRn value for each mode of operation using an internally generated clock source. Note: ATmega644 166 shows a block diagram of the clock generation logic. UBRR fosc ...
Page 167
... OSC BAUD = -------------------------------------- - ( 8 UBRRn f OSC BAUD = -------------------------------------- - ( 2 UBRRn Baud rate (in bits per second, bps) System Oscillator clock frequency Contents of the UBRRHn and UBRRLn Registers, (0-4095) Figure 17-2 for details. ATmega644 Equation for Calculating UBRR Value f OSC UBRRn ----------------------- - 1 = – 16BAUD ) OSC UBRRn ------------------- - 1 = – 8BAUD ...
Page 168
... A frame starts with the start bit followed by the least significant data bit. Then the next data bits total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can ATmega644 168 depends on the stability of the system clock source therefore recommended to ...
Page 169
... No transfers on the communication line (RxDn or TxDn). An IDLE line high. ⊕ even n 1 – ⊕ odd n 1 – Parity bit using even parity even Parity bit using odd parity odd Data bit n of the character n ATmega644 FRAME 4 [5] [6] [7] [8] [P] Sp1 [Sp2] … ⊕ ⊕ ⊕ ⊕ ⊕ ...
Page 170
... However, many applications use a fixed setting of the baud and control registers, and for these types of applications the initialization code can be placed directly in the main routine combined with initialization code for other I/O modules. ATmega644 170 (1) UBRRHn, r17 UBRRLn, r16 r16, (1< ...
Page 171
... UCSRnA,UDREn rjmp USART_Transmit ; Put data (r16) into buffer, sends the data out UDRn,r16 ret (1) /* Wait for empty transmit buffer */ while ( !( UCSRnA & (1<<UDREn Put data into buffer, sends the data */ UDRn = data; 1. See “About Code Examples” on page 8. ATmega644 171 ...
Page 172
... This bit is set when the transmit buffer is empty, and cleared when the transmit buffer contains data to be transmitted that has not yet been moved into the Shift Register. For compat- ibility with future devices, always write this bit to zero when writing the UCSRnA Register. ATmega644 172 (1)(2) ...
Page 173
... UDRn I/O location. The following code example shows a simple USART receive function based on polling of the Receive Complete (RXCn) Flag. When using frames with less than eight bits the most significant 2593N–AVR–07/10 ATmega644 173 ...
Page 174
... UDRn I/O location will change the state of the receive buffer FIFO and consequently the TXB8n, FEn, DORn and UPEn bits, which all are stored in the FIFO, will change. The following code example shows a simple USART receive function that handles both nine bit characters and the status bits. ATmega644 174 (1) r16, UDRn (1) ...
Page 175
... UCSRnA; resh = UCSRnB; resl = UDRn error, return - status & (1<<FEn)|(1<<DORn)|(1<<UPEn) ) return -1; /* Filter the 9th bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << resl); 1. See “About Code Examples” on page 8. ATmega644 175 ...
Page 176
... Check to be performed (odd or even) is selected by the UPMn0 bit. When enabled, the Parity Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together ATmega644 176 ”Parity Bit Calculation” on page 169 and ” ...
Page 177
... Note the 2593N–AVR–07/10 (1) sbis UCSRnA, RXCn ret in r16, UDRn rjmp USART_Flush (1) unsigned char dummy; while ( UCSRnA & (1<<RXCn) ) dummy = UDRn; 1. See “About Code Examples” on page 8. ATmega644 Figure 17-5 177 ...
Page 178
... RxDn pin. The recovery process is then repeated until a complete frame is received. Including the first stop bit. Note that the Receiver only uses the first stop bit of a frame. Figure 17-7 of the next frame. ATmega644 178 RxD IDLE 0 ...
Page 179
... R is the ratio of the fastest incoming data rate that can be fast accepted in relation to the receiver baud rate. and Table 17-3 list the maximum receiver baud rate error that can be tolerated. Note ATmega644 STOP 1 (A) ( ...
Page 180
... If the Receiver is set up for frames with nine data bits, then the ninth bit (RXB8n) is used for identifying address and data frames. When ATmega644 180 Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode ...
Page 181
... Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCMn bit. The MPCMn bit shares the same I/O location as the TXCn Flag and this might accidentally be cleared when using SBI or CBI instructions. 2593N–AVR–07/10 ATmega644 181 ...
Page 182
... Bit 5 – UDREn: USART Data Register Empty The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can generate a Data Register Empty interrupt (see description of the UDRIEn bit). ATmega644 182 7 6 ...
Page 183
... TXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXCn bit in UCSRnA is set. 2593N–AVR–07/10 ”Multi-processor Communication Mode” on page RXCIEn TXCIEn UDRIEn RXENn R/W R/W R/W R ATmega644 180 TXENn UCSZn2 RXB8n TXB8n R/W R UCSRnB 183 ...
Page 184
... UCSRnC – USART Control and Status Register n C Bit Read/Write Initial Value • Bits 7:6 – UMSELn1:0 USART Mode Select These bits select the mode of operation of the USARTn as shown in Table 17-4. UMSELn1 Note: ATmega644 184 UMSELn1 UMSELn0 UPMn1 R/W R/W ...
Page 185
... UPMn Bits Settings UPMn1 UPMn0 USBS Bit Settings USBSn Stop Bit(s) 0 1-bit 1 2-bit UCSZn Bits Settings UCSZn1 ATmega644 Parity Mode Disabled Reserved Enabled, Even Parity Enabled, Odd Parity UCSZn0 Character Size 0 5-bit 1 6-bit 0 7-bit 1 8-bit 0 Reserved 1 Reserved 0 Reserved 1 9-bit 185 ...
Page 186
... UBRRL contains the eight least significant bits of the USART baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is changed. Writing UBRRL will trigger an immediate update of the baud rate prescaler. ATmega644 186 UCPOLn Bit Settings ...
Page 187
... Kbps 230.4 Kbps ATmega644 Table 17-9 to ”Asynchronous ⎞ Closest Match • – 100% ⎠ 2.0000 MHz osc U2Xn = 0 Error UBRR Error UBRR 0.0% 51 0.2% 103 0.0% 25 ...
Page 188
... Max. 230.4 Kbps 460.8 Kbps 1. UBRR = 0, Error = 0.0% ATmega644 188 f = 4.0000 MHz osc U2Xn = 0 U2Xn = 1 Error UBRR Error UBRR 0.0% 103 0.2% 207 0.0% 51 0.2% 103 0.0% 25 0.2% 51 0. ...
Page 189
... Mbps 691.2 Kbps ATmega644 MHz f = 14.7456 MHz osc U2Xn = 1 U2Xn = 0 Error UBRR Error 575 0.0% 383 0.0% 287 0.0% 191 0.0% 143 0.0% 95 0. ...
Page 190
... Max. 1 Mbps 1. UBRR = 0, Error = 0.0% ATmega644 190 f = 18.4320 MHz osc U2Xn = 0 Error UBRR Error UBRR 0.0% 479 0.0% -0.1% 239 0.0% 0.2% 119 0.0% -0.1% 79 0.0% 0.2% 59 0.0% 0.6% 39 0.0% ...
Page 191
... USART in MSPIM is enabled (that is, TXENn and RXENn bit set to one). The internal clock generation used in MSPIM mode is identical to the USART synchronous mas- ter mode. The baud rate or UBRRn setting can therefore be calculated using the same equations, see 2593N–AVR–07/ XCKmax CK/2 Table 18-1: ATmega644 191 ...
Page 192
... Figure 18-1. UCPHAn and UCPOLn data transfer timing diagrams. XCK Data setup (TXD) Data sample (RXD) XCK Data setup (TXD) Data sample (RXD) ATmega644 192 Equations for Calculating Baud Rate Register Setting Equation for Calculating Baud Rate BAUD = -------------------------------------- - ( 2 UBRRn 1. The baud rate is defined to be the transfer rate in bit per second (bps) ...
Page 193
... Contrary to the normal mode USART operation the UBRRn must then be written to the desired value after the transmitter is enabled, but before the first transmission is started. Setting UBRRn to zero before enabling the transmitter is not neces- sary if the initialization is done immediately after a reset since UBRRn is reset to zero. ATmega644 193 ...
Page 194
... Receiver's serial input. The XCKn will in both cases be used as the transfer clock. After initialization the USART is ready for doing data transfers. A data transfer is initiated by writ- ing to the UDRn I/O location. This is the case for both sending and receiving data since the ATmega644 194 (1) (1) 1. See “ ...
Page 195
... UCSRnA & (1<<UDREn Put data into buffer, sends the data */ UDRn = data; /* Wait for data to be received */ while ( !(UCSRnA & (1<<RXCn Get and return received data from buffer */ return UDRn; 1. See “About Code Examples” on page 8. ATmega644 195 ...
Page 196
... Data Register Empty interrupt (see description of the UDRIE bit). UDREn is set after a reset to indicate that the Transmitter is ready. • Bit 4:0 - Reserved Bits in MSPI mode When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits must be written to zero when UCSRnA is written. ATmega644 196 ...
Page 197
... UCSRnB is written. 18.7.4 UCSRnC – USART MSPIM Control and Status Register n C Bit Read/Write Initial Value 2593N–AVR–07/ RXCIEn TXCIEn UDRIE RXENn R/W R/W R/W R UMSELn1 UMSELn0 - - R/W R ATmega644 TXENn - - - R UDORDn UCPHAn UCPOLn R R/W R/W R UCSRnB UCSRnC 197 ...
Page 198
... UBRRnL and UBRRnH –USART MSPIM Baud Rate Registers The function and bit description of the baud rate registers in MSPI mode is identical to normal USART operation. See “UBRRnL and UBRRnH – USART Baud Rate Registers” on page 186. ATmega644 198 UMSELn Bits Settings UMSELn0 ...
Page 199
... A comparison of the USART in MSPIM mode and the SPI pins is shown in 199. Table 18-4. USART_MSPIM 2593N–AVR–07/10 Comparison of USART in MSPIM mode and SPI pins. SPI TxDn MOSI RxDn MISO XCKn SCK (N/A) SS ATmega644 Table 18-4 on page Comment Master Out only Master In only (Functionally identical) Not supported by USART in MSPIM 199 ...
Page 200
... Figure 19-1. TWI Bus Interconnection 19.2.1 TWI Terminology The following definitions are frequently encountered in this section. Table 19-1. Term Master Slave Transmitter Receiver ATmega644 200 Device 1 Device 3 Device 2 SDA SCL TWI Terminology Description The device that initiates and terminates a transmission. The Master also generates the SCL clock ...