AT91SAM7L128-CU Atmel, AT91SAM7L128-CU Datasheet - Page 144
![MCU ARM7 128K HS FLASH 144-LFBGA](/photos/12/13/121356/144-lfbga_sml.jpg)
AT91SAM7L128-CU
Manufacturer Part Number
AT91SAM7L128-CU
Description
MCU ARM7 128K HS FLASH 144-LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7L64-CU.pdf
(564 pages)
Specifications of AT91SAM7L128-CU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
36MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.55 V ~ 1.8 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFBGA
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
6 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
36 MHz
Number Of Programmable I/os
80
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
For Use With
AT91SAM7L-STK - KIT EVAL FOR AT91SAM7LAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7L128-CU
Manufacturer:
Atmel
Quantity:
2 660
- Current page: 144 of 564
- Download datasheet (9Mb)
Figure 19-3. Code Read Optimization in ARM Mode for FWS = 3
Note:
Figure 19-4. Code Read Optimization in ARM Mode for FWS = 4
Note:
144
Buffer 0 (128bits)
Buffer 1 (128bits)
Buffer 0 (128bits)
Buffer 1 (128bits)
ARM Request
ARM Request
Data To ARM
Flash Access
Master Clock
Flash Access
Data To ARM
Master Clock
When FWS is included between 1 and 3, in case of sequential reads, the first access takes (FWS+1) cycles, the other ones only
1 cycle.
When FWS is included between 4 and 10, in case of sequential reads, the first access takes (FWS+1) cycles, each first access
of the 128-bit read (FWS-2) cycles, and the others only 1 cycle.
(32-bit)
AT91SAM7L128/64 Preliminary
(32-bit)
@Byte 0
@Byte 0
XXX
XXX
XXX
Bytes 0-15
Bytes 0-15
XXX
XXX
@4
0-3
XXX
@4
0-3
@8
4-7
@8
4-7
@12 @16
Bytes 16-31
8-11
@12 @16
8-11
Bytes 16-31
12-15
12-15
Bytes 0-15
@20
16-19 20-23
@24
@20
Bytes 0-15
16-19
@28 @32
Bytes 32-47
24-27
@24
20-23
28-31 32-35
@28 @32
Bytes 32-47
24-27
@36 @40
Bytes 16-31
28-31
Bytes 16-31
36-39
@44 @48 @52
6257A–ATARM–20-Feb-08
Bytes 48-63
@36 @40
Bytes 32-47
40-43
32-35
44-47
Bytes 48-63
Bytes 32-47
36-39
48-51
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