ATMEGA128-16AU Atmel, ATMEGA128-16AU Datasheet - Page 305

• Manufacturer Part Number: ATMEGA128-16AU
• Description: IC AVR MCU 128K 16MHZ 5V 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, JTAG, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 4096Byte
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPI Serial
Programming
Characteristics
Programming Via
the JTAG Interface
Programming Specific
JTAG Instructions
2467V–AVR–02/11
For characteristics of the SPI module, see
Programming through the JTAG interface requires control of the four JTAG specific pins: TCK,
TMS, TDI, and TDO. Control of the Reset and clock pins is not required.
To be able to use the JTAG interface, the JTAGEN fuse must be programmed. The device is
default shipped with the Fuse programmed. In addition, the JTD bit in MCUCSR must be
cleared. Alternatively, if the JTD bit is set, the external reset can be forced low. Then, the JTD bit
will be cleared after two chip clocks, and the JTAG pins are available for programming. This pro-
vides a means of using the JTAG pins as normal port pins in running mode while still allowing In-
System Programming via the JTAG interface. Note that this technique can not be used when
using the JTAG pins for Boundary-scan or On-chip Debug. In these cases the JTAG pins must
be dedicated for this purpose.
As a definition in this data sheet, the LSB is shifted in and out first of all Shift Registers.
The instruction register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions
useful for Programming are listed below.
The OPCODE for each instruction is shown behind the instruction name in hex format. The text
describes which data register is selected as path between TDI and TDO for each instruction.
The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be
used as an idle state between JTAG sequences. The state machine sequence for changing the
instruction word is shown in
Figure
146.
“SPI Timing Characteristics” on page
ATmega128
323.
305