ATMEGA128-16AU Atmel, ATMEGA128-16AU Datasheet - Page 323

• Manufacturer Part Number: ATMEGA128-16AU
• Description: IC AVR MCU 128K 16MHZ 5V 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, JTAG, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 4096Byte
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPI Timing
Characteristics
2467V–AVR–02/11
5. This requirement applies to all
the Two-wire Serial Bus need only obey the general f
Figure 154. Two-wire Serial Bus Timing
See
Table 134. SPI Timing Parameters
Note:
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
Figure 155
SCL
SDA
1. In SPI Programming mode the minimum SCK high/low period is:
SS high to tri-state
SCK to out high
SCK to SS high
- 2 t
- 3 t
t
SCK high/low
SS low to SCK
SU;STA
SCK high/low
Rise/Fall time
Rise/Fall time
SS low to out
Description
Atmel
SCK period
Out to SCK
SCK period
SCK to out
SCK to out
CLCL
CLCL
Setup
Setup
and
Hold
Hold
®
for f
for f
AVR
Figure 156
CK
CK
(1)
®
< 12MHz
>12MHz
ATmega128 Two-wire Serial Interface operation. Other devices connected to
t
HD;STA
t
of
t
LOW
for details.
SCL
Master
Master
Master
Master
Master
Master
Master
Master
Mode
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
requirement.
t
HIGH
t
HD;DAT
4 • t
2 • t
2 • t
Min
10
10
20
ck
ck
ck
t
LOW
t
SU;DAT
50% duty cycle
See
0.5 • t
Table 72
Typ
3.6
10
10
10
10
15
15
10
sck
ATmega128
t
SU;STO
Max
1.6
t
r
ns
µs
ns
t
BUF
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