P87LPC762FD,512 NXP Semiconductors, P87LPC762FD,512 Datasheet - Page 30

• Manufacturer Part Number: P87LPC762FD,512
• Description: IC 80C51 MCU 2K OTP 20-SOIC
• Manufacturer: NXP Semiconductors
• Series: LPC700r

Specifications of P87LPC762FD,512

• Program Memory Type: OTP
• Program Memory Size: 2KB (2K x 8)
• Package / Case: 20-SOIC (7.5mm Width)
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, WDT
• Number Of I /o: 18
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P87LPC7x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C/UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 45 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: OM10063 - PROGRAMMER LPC700 P76XLCPOM10050 - EMULATOR LPC700 PDS76X
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-3212-5; 935266853512; P87LPC762FD

Philips Semiconductors
Low Voltage EPROM Operation
The EPROM array contains some analog circuits that are not
required when V
greater than 4 V. The LPEP bit (AUXR.4), when set by software, will
power down these analog circuits resulting in a reduced supply
current. LPEP is cleared only by power-on reset, so it may be set
ONLY for applications that always operate with V
Reset
The 87LPC762 has an integrated power-on reset circuit which
always provides a reset when power is initially applied to the device.
It is recommended to use the internal reset whenever possible to
2001 Oct 26
Low power, low price, low pin count (20 pin)
microcontroller with 2 kbyte OTP
SOFTWARE RESET
POWER MONITOR
SRST (AUXR1.3)
DD
UCFG1.RPD = 1 (default)
WDTE (UCFG1.7)
MODULE
RPD (UCFG1.6)
is less than 4 V, but are required for a V
RESET
WDT
RST/V
PP
Figure 20. Using pin P1.5 as general purpose input pin or as low-active reset pin
PIN
P1.5
Pin is used as
digital input pin
Internal power-on
Reset active
87LPC762
Figure 21. Block Diagram Showing Reset Sources
DD
less than 4 V.
DD
UCFG1.RPD = 0
27
external active-low reset pin RST by programming the RPD bit in the
save external components and to be able to use pin P1.5 as a
general-purpose input pin.
The 87LPC762 can additionally be configured to use P1.5 as an
User Configuration Register UCFG1 to 0. The internal reset is still
active on power-up of the device. While the signal on the RST pin is
low, the 87LPC762 is held in reset until the signal goes high.
The watchdog timer on the LPC762 can act as an oscillator fail
detect because it uses an independent, fully on-chip oscillator.
UCFG1 is described in the System Configuration Bytes section of
this datasheet.
CLOCK
CPU
RST
Pin is used as
active-low reset pin
Internal power-on
Reset active
RESET
TIMING
87LPC762
R
S
Q
SU01226
CHIP RESET
87LPC762
SU01170
Preliminary data