LPC3250FET296,551 NXP Semiconductors, LPC3250FET296,551 Datasheet - Page 37
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LPC3250FET296,551
Manufacturer Part Number
LPC3250FET296,551
Description
IC ARM9 MCU 256K 296-TFBGA
Manufacturer
NXP Semiconductors
Series
LPC32x0r
Datasheet
1.OM11079.pdf
(77 pages)
Specifications of LPC3250FET296,551
Core Processor
ARM9
Core Size
16/32-Bit
Speed
266MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, Motor Control PWM, PWM, WDT
Number Of I /o
51
Program Memory Type
ROMless
Ram Size
256K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 3.6 V
Data Converters
A/D 3x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
296-TFBGA
Processor Series
LPC32
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
256 KB
Interface Type
I2C, I2S, UART, USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
51
Number Of Timers
6
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, DK-57TS-LPC3250, DK-57VTS-LPC3250, SOMDIMM-LPC3250
Development Tools By Supplier
OM11016, OM11021, OM11045
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
OM11021 - EVAL LPC-STICK WITH LPC3250OM11016 - KIT DEVELOPMENT LPC3250568-4743 - KIT LCD TOUCH 5.7" FOR LPC3250568-4742 - MODULE DIMM LPC2478 ARM7622-1030 - KIT LCD TOUCH 5.7" FOR LPC3250
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4533
935287084551
935287084551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC3250FET296,551
Manufacturer:
BONENS
Quantity:
98
Company:
Part Number:
LPC3250FET296,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
LPC3220_30_40_50_1
Product data sheet
7.8.2.1 Features
7.8.3.1 Features
7.8.3 SSP serial I/O controller
7.8.4 I
Only a single master and a single slave can communicate on the interface during a given
data transfer. During a data transfer the master always sends a byte of data to the slave,
and the slave always sends a byte of data to the master. The SPI implementation on the
LPC3220/30/40/50 does not support operation as a slave.
The LPC3220/30/40/50 contains two SSP controllers. The SSP controller is capable of
operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and
slaves on the bus. Only a single master and a single slave can communicate on the bus
during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits
to 16 bits of data flowing from the master to the slave and from the slave to the master. In
practice, often only one of these data flows carries meaningful data.
There are two I
can be configured as a master, multi-master or slave supporting up to 400 kHz. The I
blocks also support 7 or 10 bit addressing. Each has a four word FIFO for both transmit
and receive. An interrupt signal is available from each block.
2
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C-bus serial I/O controller
Supports slaves compatible with SPI modes 0 to 3.
Half duplex synchronous transfers.
DMA support for data transmit and receive.
1-bit to 16-bit word length.
Choice of LSB or MSB first data transmission.
64 × 16-bit input or output FIFO.
Bit rates up to 52 Mbit/s.
Busy input function.
DMA time out interrupt to allow detection of end of reception when using DMA.
Timed interrupt to facilitate emptying the FIFO at the end of a transmission.
SPI clock and data pins may be used as general purpose pins if the SPI is not used.
Slave selects can be supported using GPO or GPIO pins
Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire
buses
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
Maximum SPI bus data bit rate of
clock rate
DMA transfers supported by GPDMA
2
All information provided in this document is subject to legal disclaimers.
C-bus interfaces in the LPC32x0 family of controllers. These I
Rev. 01.03 — 16 March 2010
1
⁄
2
(Master mode) and
LPC3220/30/40/50
16/32-bit ARM microcontrollers
1
⁄
12
(Slave mode) of the input
© NXP B.V. 2010. All rights reserved.
2
C blocks
37 of 77
2
C