LPC2141FBD64,151 NXP Semiconductors, LPC2141FBD64,151 Datasheet - Page 21

• Manufacturer Part Number: LPC2141FBD64,151
• Description: IC ARM7 MCU FLASH 32K 64LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2100r

Specifications of LPC2141FBD64,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 64-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 60MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 45
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC21
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/UART/SPI/SSP/I2C/USB
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 45
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 10-bit
• Cpu Family: LPC2000
• Device Core: ARM7TDMI-S
• Device Core Size: 16/32Bit
• Frequency (max): 60MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 45
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Package: 64LQFP
• Family Name: LPC2000
• Maximum Speed: 60 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4310 - EVAL BOARD LPC2158 W/LCD568-4297 - BOARD EVAL LPC21XX MCB2100MCB2140UME - BOARD EVAL MCB2140 + ULINK-MEMCB2140U - BOARD EVAL MCB2140 + ULINK2MCB2140 - BOARD EVAL NXP LPC214X ARM FAM622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K568-2097 - BOARD EVAL FOR LPC214X ARM MCU
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1761; 935280015151; LPC2141FBD64-S

NXP Semiconductors
LPC2141_42_44_46_48_4
Product data sheet
6.18.1 Features
6.18 Pulse width modulator
The PWM is based on the standard timer block and inherits all of its features, although
only the PWM function is pinned out on the LPC2141/42/44/46/48. The timer is designed
to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or
perform other actions when specified timer values occur, based on seven match registers.
The PWM function is also based on match register events.
The ability to separately control rising and falling edge locations allows the PWM to be
used for more applications. For instance, multi-phase motor control typically requires three
non-overlapping PWM outputs with individual control of all three pulse widths and
positions.
Two match registers can be used to provide a single edge controlled PWM output. One
match register (MR0) controls the PWM cycle rate, by resetting the count upon match.
The other match register controls the PWM edge position. Additional single edge
controlled PWM outputs require only one match register each, since the repetition rate is
the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a
rising edge at the beginning of each PWM cycle, when an MR0 match occurs.
Three match registers can be used to provide a PWM output with both edges controlled.
Again, the MR0 match register controls the PWM cycle rate. The other match registers
control the two PWM edge positions. Additional double edge controlled PWM outputs
require only two match registers each, since the repetition rate is the same for all PWM
outputs.
With double edge controlled PWM outputs, specific match registers control the rising and
falling edge of the output. This allows both positive going PWM pulses (when the rising
edge occurs prior to the falling edge), and negative going PWM pulses (when the falling
edge occurs prior to the rising edge).
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Seven match registers allow up to six single edge controlled or three double edge
controlled PWM outputs, or a mix of both types.
The match registers also allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Supports single edge controlled and/or double edge controlled PWM outputs. Single
edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the
output is a constant LOW. Double edge controlled PWM outputs can have either edge
occur at any position within a cycle. This allows for both positive going and negative
going pulses.
Pulse period and width can be any number of timer counts. This allows complete
flexibility in the trade-off between resolution and repetition rate. All PWM outputs will
occur at the same repetition rate.
Double edge controlled PWM outputs can be programmed to be either positive going
or negative going pulses.
Rev. 04 — 17 November 2008
LPC2141/42/44/46/48
Single-chip 16-bit/32-bit microcontrollers
© NXP B.V. 2008. All rights reserved.
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