LPC2141FBD64,151 NXP Semiconductors, LPC2141FBD64,151 Datasheet - Page 23
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LPC2141FBD64,151
Manufacturer Part Number
LPC2141FBD64,151
Description
IC ARM7 MCU FLASH 32K 64LQFP
Manufacturer
NXP Semiconductors
Series
LPC2100r
Datasheet
1.LPC2141FBD64151.pdf
(40 pages)
Specifications of LPC2141FBD64,151
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
64-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
60MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
45
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC21
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
8 KB
Interface Type
SCI/UART/SPI/SSP/I2C/USB
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
45
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 10-bit
Cpu Family
LPC2000
Device Core
ARM7TDMI-S
Device Core Size
16/32Bit
Frequency (max)
60MHz
Total Internal Ram Size
8KB
# I/os (max)
45
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
LQFP
Package
64LQFP
Family Name
LPC2000
Maximum Speed
60 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4310 - EVAL BOARD LPC2158 W/LCD568-4297 - BOARD EVAL LPC21XX MCB2100MCB2140UME - BOARD EVAL MCB2140 + ULINK-MEMCB2140U - BOARD EVAL MCB2140 + ULINK2MCB2140 - BOARD EVAL NXP LPC214X ARM FAM622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K568-2097 - BOARD EVAL FOR LPC214X ARM MCU
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Other names
568-1761
935280015151
LPC2141FBD64-S
935280015151
LPC2141FBD64-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2141FBD64,151
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
LPC2141_42_44_46_48_4
Product data sheet
6.19.4 Brownout detector
6.19.5 Code security
6.19.6 External interrupt inputs
6.19.7 Memory mapping control
The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is
safe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufficient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of V
and its electrical characteristics (if a quartz crystal is used), as well as any other external
circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing
ambient conditions.
The LPC2141/42/44/46/48 include 2-stage monitoring of the voltage on the V
this voltage falls below 2.9 V, the BOD asserts an interrupt signal to the VIC. This signal
can be enabled for interrupt; if not, software can monitor the signal by reading dedicated
register.
The second stage of low voltage detection asserts reset to inactivate the
LPC2141/42/44/46/48 when the voltage on the V
prevents alteration of the flash as operation of the various elements of the chip would
otherwise become unreliable due to low voltage. The BOD circuit maintains this reset
down below 1 V, at which point the POR circuitry maintains the overall reset.
Both the 2.9 V and 2.6 V thresholds include some hysteresis. In normal operation, this
hysteresis allows the 2.9 V detection to reliably interrupt, or a regularly-executed event
loop to sense the condition.
This feature of the LPC2141/42/44/46/48 allow an application to control whether it can be
debugged or protected from observation.
If after reset on-chip boot loader detects a valid checksum in flash and reads 0x8765 4321
from address 0x1FC in flash, debugging will be disabled and thus the code in flash will be
protected from observation. Once debugging is disabled, it can be enabled only by
performing a full chip erase using the ISP.
The LPC2141/42/44/46/48 include up to nine edge or level sensitive External Interrupt
Inputs as selectable pin functions. When the pins are combined, external events can be
processed as four independent interrupt signals. The External Interrupt Inputs can
optionally be used to wake-up the processor from Power-down mode.
Additionally capture input pins can also be used as external interrupts without the option
to wake the device up from Power-down mode.
The Memory Mapping Control alters the mapping of the interrupt vectors that appear
beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip
flash memory, or to the on-chip static RAM. This allows code running in different memory
spaces to have control of the interrupts.
Rev. 04 — 17 November 2008
DD
ramp (in the case of power on), the type of crystal
LPC2141/42/44/46/48
Single-chip 16-bit/32-bit microcontrollers
DD
pins falls below 2.6 V. This reset
© NXP B.V. 2008. All rights reserved.
DD
pins. If
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