LPC3131FET180,551 NXP Semiconductors, LPC3131FET180,551 Datasheet
LPC3131FET180,551
Specifications of LPC3131FET180,551
935288014551
LPC3131FET180-S
Available stocks
Related parts for LPC3131FET180,551
LPC3131FET180,551 Summary of contents
Page 1
LPC3130/3131 Low-cost, low-power ARM926EJ-S MCUs with high-speed USB 2.0 OTG, SD/MMC, and NAND flash controller Rev. 1.04 — 27 May 2010 1. General description The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB 2.0 On-The-Go (OTG), up ...
Page 2
... NXP Semiconductors Four 32-bit timers Watchdog timer PWM module Random Number Generator (RNG) General Purpose I/O (GPIO) pins Flexible and versatile interrupt structure JTAG interface with boundary scan and ARM debug access Operating voltage and temperature Core voltage: 1.2 V I/O voltage: 1.8 V, 3.3 V Temperature: − ...
Page 3
... NXP Semiconductors 4. Block diagram JTAG interface TEST/DEBUG INTERFACE ARM926EJ-S master slave INTERRUPT CONTROLLLER slave MPMC slave slave MCI SD/SDIO AHB TO APB BRIDGE 0 ASYNC APB slave group 0 WDT SYSTEM CONTROL CGU IOCONFIG 10-bit ADC EVENT ROUTER RANDOM NUMBER GENERATOR APB slave group 1 ...
Page 4
... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. LPC3130/3131 pinning TFBGA180 package Table 3. Pin allocation table Pin Symbol Pin Symbol Row A 1 EBI_D_10 2 EBI_A_1_CLE 5 mGPIO7 6 mGPIO6 9 VDDI 10 FFAST_IN 13 ADC10B_VDDA33 14 ADC10B_GPA1 Row B 1 EBI_D_8 2 VDDE_IOA 5 mGPIO8 6 mGPIO5 9 PWM_DATA 10 FFAST_OUT 13 ADC10B_GPA2 14 ADC10B_GPA0 Row C 1 EBI_D_7 ...
Page 5
... NXP Semiconductors Table 3. Pin allocation table …continued Pin Symbol Pin Symbol Row E 1 EBI_D_3 2 EBI_D_4 5 VDDE_IOA 6 mNAND_RYBN0 9 VSSA12 10 VDDA12 13 I2C_SCL1 14 I2STX_BCK1 Row F 1 EBI_D_2 2 EBI_D_1 5 VDDE_IOA 10 SCAN_TDO 13 I2SRX_WS1 14 I2SRX_BCK1 Row G 1 EBI_NCAS_BLOUT_0 2 EBI_D_0 5 VDDE_IOA 10 I2STX_WS1 13 SYSCLK_O 14 I2SRX_DATA1 Row H 1 EBI_DQM_0_NOE 2 EBI_NRAS_BLOUT_1 ...
Page 6
... NXP Semiconductors Table 3. Pin allocation table …continued Pin Symbol Pin Symbol Row P 1 USB_VDDA33 2 USB_DP 5 mLCD_DB_7 6 mLCD_DB_3 9 mLCD_DB_1 10 TMS 13 TRST_N 14 mUART_RTS_N Table 4. Pin description Pin names with prefix m are multiplexed pins. See Pin name BGA Digital ball I/O level [1] Clock Generation Unit ...
Page 7
... NXP Semiconductors Table 4. Pin description Pin names with prefix m are multiplexed pins. See Pin name BGA Digital ball I/O level [1] USB_DM N2 SUP3 USB_VDDA12_PLL L1 SUP1 USB_VDDA33_DRV M2 SUP3 USB_VDDA33 P1 SUP3 USB_VSSA_TERM L3 USB_GNDA N1 USB_VSSA_REF K4 JTAG JTAGSEL N11 SUP3 TDI K9 SUP3 TRST_N P13 SUP3 TCK ...
Page 8
... NXP Semiconductors Table 4. Pin description Pin names with prefix m are multiplexed pins. See Pin name BGA Digital ball I/O level [1] Serial Peripheral Interface [4] SPI_CS_OUT0 A7 SUP3 [4] SPI_SCK A8 SUP3 [4] SPI_MISO C8 SUP3 [4] SPI_MOSI B7 SUP3 [4] SPI_CS_IN B8 SUP3 Digital power supply VDDI H3; SUP1 L7; L12; C12; C6; ...
Page 9
... NXP Semiconductors Table 4. Pin description Pin names with prefix m are multiplexed pins. See Pin name BGA Digital ball I/O level [1] VSSE_IOB M3; M4; M6; M8 VSSE_IOC B12; D6; D8; D9; G11; L9; L13 LCD Interface [4] mLCD_CSB K8 SUP8 [4] mLCD_E_RD L8 SUP8 [4] mLCD_RS P8 SUP8 [4] mLCD_RW_WR N9 SUP8 [4] mLCD_DB_0 N8 SUP8 [4] mLCD_DB_1 ...
Page 10
... NXP Semiconductors Table 4. Pin description Pin names with prefix m are multiplexed pins. See Pin name BGA Digital ball I/O level [ S/Digital Audio Input [4] I2SRX_DATA0 M10 SUP3 [4] I2SRX_DATA1 G14 SUP3 [4] I2SRX_BCK0 N10 SUP3 [4] I2SRX_BCK1 F14 SUP3 [4] I2SRX_WS0 P11 SUP3 [4] I2SRX_WS1 F13 SUP3 ...
Page 11
... NXP Semiconductors Table 4. Pin description Pin names with prefix m are multiplexed pins. See Pin name BGA Digital ball I/O level [1] External Bus Interface (NAND flash controller) [4] EBI_A_0_ALE B3 SUP4 [4] EBI_A_1_CLE A2 SUP4 [4] EBI_D_0 G2 SUP4 [4] EBI_D_1 F2 SUP4 [4] EBI_D_2 F1 SUP4 [4] EBI_D_3 E1 SUP4 [4] EBI_D_4 E2 SUP4 [4] EBI_D_5 ...
Page 12
... NXP Semiconductors [5] The UART flow control lines (mUART_CTS_N and mUART_RTS_N) are multiplexed. This means that if these balls are not required for UART flow control, they can also be selected to be used for an alternative function: SPI chip select signals (SPI_CS_OUT1 and SPI_CS_OUT2). [6] To ensure that GPIO0, GPIO1 and GPIO2 pins come up as inputs, pins TRST_N and JTAGSEL must be LOW at power-on reset, see UM10314 JTAG chapter for details ...
Page 13
... NXP Semiconductors 6. Functional description 6.1 ARM926EJ-S The processor embedded in the LPC3130/3131 is the ARM926EJ- member of the ARM9 family of general-purpose microprocessors. The ARM926EJ-S is intended for multi-tasking applications where full memory management, high performance, and low power are important. This module has the following features: • ...
Page 14
... NXP Semiconductors 6.2 Memory map LPC3130/3131 4 GB reserved 2 GB reserved NAND buffer reserved interrupt controller reserved external SDRAM bank 0 external SRAM bank 1 external SRAM bank 0 reserved USB OTG reserved MCI/SD/SDIO reserved MPMC configuration registers APB4 domain APB3 domain APB2 domain reserved ...
Page 15
... NXP Semiconductors 6.3 JTAG The Joint Test Action Group (JTAG) interface allows the incorporation of the LPC3130/3131 in a JTAG scan chain. This module has the following features: • ARM926 debug access • Boundary scan 6.4 NAND flash controller The NAND flash controller is used as a dedicated interface to NAND flash devices. ...
Page 16
... NXP Semiconductors • Software control mode where the ARM is directly master of the flash device. • Support for 8 bit and 16 bit flash devices. • Support for any page size from 0.5 kB upwards. • Programmable NAND flash timing parameters. • Support for NAND devices. ...
Page 17
... NXP Semiconductors – extended wait • One chip select for synchronous memory and two chip selects for static memory devices. • Power-saving modes. • Dynamic memory self-refresh mode supported. • Controller support for and 8 k row address synchronous memory parts. • ...
Page 18
... NXP Semiconductors Table 8. LPC3130/3131 boot modes Boot mode NAND SPI DFU SD/MMC Reserved 0 NOR flash UART Test 6.8 Internal RAM memory The ISRAM (Internal Static RAM Memory) controller module is used as controller between the AHB bus and the internal RAM memory. The internal RAM memory can be used as ...
Page 19
... NXP Semiconductors • Supports 1/4-bit SD cards. • Card detection and write protection. • FIFO buffers of 16 bytes deep. • Host pull-up control. • SDIO suspend and resume. • 535 bytes blocks. • Suspend and resume operations. • SDIO Read-wait. • Maximum clock speed of 52 MHz (MMC 4.1). ...
Page 20
... NXP Semiconductors – Memory can be copied from the source address to the destination address with a specified length, while incrementing the address for both the source and destination. Memory to peripheral: – Data is transferred from incrementing memory to a fixed address of a peripheral. The flow is controlled by the peripheral. ...
Page 21
... NXP Semiconductors • Visibility of the interrupt’s request state before masking. • Support for nesting of interrupt service routines. • Interrupts routed to IRQ and to FIQ are vectored. • Level interrupt support. The following blocks can generate interrupts: • NAND flash controller • ...
Page 22
... NXP Semiconductors ARM DMA 926EJ-S masters AHB MULTILAYER MATRIX = master/slave connection supported by matrix (1) LPC3131 only. Fig 5. LPC3130/3131 multi-layer AHB matrix connections This module has the following features: LPC3130_3131 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers USB-OTG AHB MASTER 3 asynchronous slaves bridge ...
Page 23
... NXP Semiconductors • Supports all combinations of 32-bit masters and slaves (fully connected interconnect matrix). • Round-robin priority mechanism for bus arbitration: all masters have the same priority and get bus access in their natural order • Four devices on a master port (listed in their natural order for bus arbitration): – ...
Page 24
... NXP Semiconductors Within most clock domains, the output clocks are again grouped into one or more subdomains. All output clocks within one subdomain are either all generated by the same fractional divider or they are connected directly to the base clock. Therefore all output clocks within one subdomain have the same frequency and all output clocks within one clock domain are synchronous because they originate from the same base clock ...
Page 25
... NXP Semiconductors • Based on the input of the Watchdog timer (see also generate a system-wide reset in the case of a system stall. clock resources EXTERNAL OSCILLATOR CRYSTAL I2SRX_BCK0 I2SRX_WS0 I2SRX_BCK1 I2SRX_WS1 The LPC3130/3131 has 11 clock domains (n = 11). The number of fractional dividers m depends on the clock domain. ...
Page 26
... NXP Semiconductors APB Fig 7. Block diagram of the Watchdog timer 6.17 Input/Output configuration module (IOCONFIG) The General Purpose Input/Output (GPIO) pins can be controlled through the register interface provided in the IOCONFIG module. Next to several dedicated GPIO pins, most digital I/O pins can also be used as GPIO if they are not required for their normal, dedicated function ...
Page 27
... NXP Semiconductors 6.19 Event router The event router extends the interrupt capability of the system by offering a flexible and versatile way of generating interrupts. Combined with the wake-up functionality of the CGU, it also offers a way to wake up the system from suspend mode (with all clocks deactivated). ...
Page 28
... NXP Semiconductors 6.20 Random number generator The Random Number Generator (RNG) generates true random numbers for use in advanced security and Digital Rights Management (DRM) related schemes. These schemes rely upon truly random, i.e. completely unpredictable numbers. This module has the following features: • ...
Page 29
... NXP Semiconductors • SIR-IrDA encoder/decoder (from 2400 to 115 kBd). • Supports maskable interrupts. • Supports DMA transfers. 6.23 Pulse Code Modulation (PCM) interface The PCM interface supports the PCM and IOM interfaces. The IOM (ISDN Oriented Modular) interface is primarily used to interconnect telecommunications ICs providing ISDN compatibility ...
Page 30
... NXP Semiconductors 2 6.25 I C-bus master/slave interface The LPC3130/3131 contains two I This module has the following features: • I2C-bus interface 0 (I2C0): I2C0 is a standard I open-drain pins. This interface supports functions described in the I specification for speeds up to 400 kHz. This includes multi-master operation and allows powering off this device in a working system while leaving the I functional ...
Page 31
... NXP Semiconductors 6.26.1 Pin connections Table 10. Pin descriptions of multiplexed pins Pin Name Default Signal Alternate Signal Video related pin multiplexing mLCD_CSB LCD_CSB EBI_NSTCS_0 LCD_CSB — LCD chip select for external LCD controller. mLCD_DB_1 LCD_DB_1 EBI_NSTCS_1 LCD_DB_1 — LCD bidirectional data line 1. ...
Page 32
... NXP Semiconductors Table 10. Pin descriptions of multiplexed pins Pin Name Default Signal Alternate Signal mLCD_DB_15 LCD_DB_15 EBI_A_15 Storage related pin multiplexing mGPIO5 GPIO5 MCI_CLK mGPIO6 GPIO6 MCI_CMD mGPIO7 GPIO7 MCI_DAT_0 mGPIO8 GPIO8 MCI_DAT_1 mGPIO9 GPIO9 MCI_DAT_2 mGPIO10 GPIO10 MCI_DAT_3 NAND related pin multiplexing ...
Page 33
... NXP Semiconductors 6.26.2 Multiplexing between LCD and MPMC The multiplexing between the LCD interface and MPMC allows for the following two modes of operation: • MPMC-mode: SDRAM and bus-based LCD or SRAM. • LCD-mode: Dedicated LCD-Interface. The external NAND flash is accessible in both modes. ...
Page 34
... NXP Semiconductors The EBI unit between the NAND flash interface and the MPMC contains an arbiter that determines which interface is muxed to the outside world. Both NAND flash and SDRAM/SRAM initiate a request to the EBI unit. This request is granted using round-robin arbitration (see 6.26.3 Supply domains As is shown in different supply domain than the LCD interface ...
Page 35
... NXP Semiconductors 6.29 System control registers The System Control Registers (SysCReg) module provides a register interface for some of the high-level settings in the system such as multiplexers and mode settings. This is an auxiliary module included in this overview for the sake of completeness. 6.30 I2S0/1 interfaces The I2S0/1 receive and I2S0/1 transmit modules have the following features: • ...
Page 36
... NXP Semiconductors 7. Limiting values Table 11. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter All digital I/O pins V input voltage I V output voltage O I output current O Temperature values T junction temperature j T storage temperature stg T ambient temperature amb ...
Page 37
... NXP Semiconductors 8. Static characteristics Table 12: Static characteristics − ° ° +85 C unless otherwise specified. amb Symbol Parameter Supply pins V input/output supply DD(IO) voltage V core supply voltage DD(CORE) V oscillator and PLL DD(OSC_PLL) supply voltage V ADC supply voltage DD(ADC) V bus supply voltage BUS ...
Page 38
... NXP Semiconductors Table 12: Static characteristics − ° ° +85 C unless otherwise specified. amb Symbol Parameter I pull-up current pu I pull-down current pd C input capacitance i Output pins and I/O pins configured as output V output voltage O V HIGH-level output OH voltage V LOW-level output OL voltage I HIGH-level output ...
Page 39
... NXP Semiconductors Table 12: Static characteristics − ° ° +85 C unless otherwise specified. amb Symbol Parameter I HIGH-level OHS short-circuit output current I LOW-level OLS short-circuit output current Z output impedance C0-bus pins I OFF-state output OZ current V HIGH-level input IH voltage V LOW-level input IL voltage V hysteresis voltage hys ...
Page 40
... NXP Semiconductors Table 13. ADC static characteristics − ° 2 3 DD(ADC) amb Symbol Parameter V analog input voltage IA C analog input capacitance ia N ADC resolution res(ADC) E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error G E absolute error T V offset error voltage ...
Page 41
... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error ( (4) Integral non-linearity (E ). L(adj) (5) Center of a step of the actual transfer curve. Fig 10. ADC characteristics LPC3130_3131 Preliminary data sheet ...
Page 42
... NXP Semiconductors Fig 11. Suggested 10-bit ADC interface LPC3130_3131 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers LPC31XX tbd kΩ ADC SAMPLE tbd pF tbd pF V SSA All information provided in this document is subject to legal disclaimers. Rev. 1.04 — 27 May 2010 LPC3130/3131 R vsi AD10B_GPA[0:3] V EXT 002aae136 © ...
Page 43
... NXP Semiconductors 8.1 Power consumption Table 14. Power consumption Symbol Parameter Conditions [1] Standby power mode I Supply current core; VDDI = 1 all other SUP1 supplies: VDDA12 = 1.2 V; USB_VDDA12_PL = 1.2 V VDDE_IOA = 1.8 V VDDE_IOB = 1.8 V VDDE_IOC = 3.3 v ADC10B_VDDA33 = 3.3 V USB_VDDA33 = 3.3 V USB_VDDA_DRV = 3 Power dissipation Total for supply domains SUP1, SUP3, SUP4, SUP8 External SDRAM based system (operating frequency 180 MHz (core)/ 90 MHz (bus)) ...
Page 44
... NXP Semiconductors Table 14. Power consumption …continued Symbol Parameter Conditions External SDRAM based system (operating frequency 180 MHz (core)/ 90 MHz (bus)); normal mode power; without [4] dynamic clock scaling I Supply current core; VDDI = 1 all other SUP1 supplies: VDDA12 = 1.2 V; USB_VDDA12_PL = 1.2 V VDDE_IOA = 1.8 V VDDE_IOB = 1 ...
Page 45
... NXP Semiconductors Table 14. Power consumption …continued Symbol Parameter Conditions Internal SRAM based system (operating frequency 180 MHz (core)/ 90 MHz (bus)); normal mode power; without [6] dynamic clock scaling; MMU off I Supply current core; VDDI = 1 all other SUP1 supplies: VDDA12 = 1.2 V; USB_VDDA12_PL = 1.2 V VDDE_IOA = 1 ...
Page 46
... NXP Semiconductors 9. Dynamic characteristics 9.1 LCD controller 9.1.1 Intel 8080 mode Table 15. Dynamic characteristics: LCD controller in Intel 8080 mode pF amb Symbol Parameter t address set-up time su(A) t address hold time h(A) t access cycle time cy(a) t write enable pulse width w(en)W t read enable pulse width ...
Page 47
... NXP Semiconductors 9.1.2 Motorola 6800 mode Table 16. Dynamic characteristics: LCD controller in Motorola 6800 mode pF amb Symbol Parameter t address set-up time su(A) t address hold time h(A) t access cycle time cy(a) t rise time r t fall time f t data input set-up time su(D) t data input hold time ...
Page 48
... NXP Semiconductors 9.1.3 Serial mode Table 17. Dynamic characteristics: LCD controller serial mode pF amb Symbol Parameter T clock cycle time cy(clk) t HIGH clock pulse width w(clk)H t LOW clock pulse width w(clk)L t rise time r t fall time f t address set-up time su(A) t address hold time ...
Page 49
... NXP Semiconductors 9.2 SRAM controller Table 18. Dynamic characteristics: static external memory interface − ° ° pF +85 C, unless otherwise specified amb Symbol Parameter Common to read and write cycles t CS LOW to address valid CSLAV time Read cycle parameters t OE LOW to address valid OELAV ...
Page 50
... NXP Semiconductors EBI_NSTCS_X t CSLAV EBI_A_[15:0] EBI_DQM_0_NOE t t EBI_NCAS_BLOUT_0 EBI_NRAS_BLOUT_1 t EBI_D_[15:0] Fig 15. External memory read access to static memory LPC3130_3131 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers t OELAV t OELOEH CSLOEL BLSLAV t BLSLBLSH CSLBLSL All information provided in this document is subject to legal disclaimers. Rev. 1.04 — 27 May 2010 ...
Page 51
... NXP Semiconductors EBI_NSTCS_X EBI_A_[15:0] EBI_D_[15:0] EBI_NWE EBI_NCAS_BLOUT_0 EBI_NRAS_BLOUT_1 Fig 16. External memory write access to static memory LPC3130_3131 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers t CSLAV t CSLDV t WELWEH t CSLWEL t WELDV t BLSLBLSH t CSLBLSL All information provided in this document is subject to legal disclaimers. Rev. 1.04 — 27 May 2010 ...
Page 52
... NXP Semiconductors 9.3 SDRAM controller Table 19. Dynamic characteristics of SDR SDRAM memory interface − ° ° +85 C, unless otherwise specified; V amb Symbol Parameter Conditions f operating frequency oper T clock cycle time CLCL t clock LOW time CLCX t clock HIGH time CHCX t output delay time ...
Page 53
... NXP Semiconductors T CLCL t CHCX EBI_CLKOUT EBI_NRAS_BLOUT EBI_NCAS_BLOUT EBI_NWE EBI_CKE EBI_NDYCS EBI_DQMx EBI_A_[15:2] EBI_D_[15:0] EBI_CKE is HIGH. Fig 17. SDRAM burst read timing LPC3130_3131 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers t CLCX t t d(o) h(o) READ NOP NOP NOP t d(o) t h(A) BANK su(D) h(D) ...
Page 54
T CLCL t CLCX t CHCX EBI_CLKOUT EBI_CKE EBI_NRAS_BLOUT EBI_NCAS_BLOUT EBI_NWE EBI_CKE EBI_NDYCS EBI_DQMx EBI_A_[15:2] EBI_D_[15:0] Fig 18. SDRAM bank activate and write timing t ...
Page 55
... NXP Semiconductors 9.4 NAND flash memory controller Table 20. Dynamic characteristics of the NAND flash memory controller − ° +85 amb Symbol t REH CLS t CLH t ALS t ALH [ 1/NANDFLASH_NAND_CLK, see LPC3130/3131 user manual. HCLK [2] See registers NandTiming1 and NandTiming2 in the LPC3130/3131 user manual. [3] Each timing parameter can be set from 7 nand_clk clock cycles to 1 nand_clk clock cycle. (A programmed zero value is treated as a one) ...
Page 56
... NXP Semiconductors 9.5 Crystal oscillator Table 21: Dynamic characteristics: crystal oscillator Symbol Parameter f oscillator frequency osc δ clock duty cycle clk C crystal capacitance xtal t start-up time startup P drive power drive 9.6 SPI Table 22. Dynamic characteristics of SPI pins − ° +85 amb Symbol Parameter ...
Page 57
... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 20. SPI master timing (CPHA = 1) Fig 21. SPI master timing (CPHA = 0) LPC3130_3131 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers T SPICYC t SPIQV DATA VALID MOSI MISO DATA VALID T SPICYC SCK (CPOL = 0) SCK (CPOL = 1) t SPIQV DATA VALID ...
Page 58
... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 22. SPI slave timing (CPHA = 1) Fig 23. SPI slave timing (CPHA = 0) LPC3130_3131 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers T SPICYC MOSI DATA VALID t SPIQV MISO DATA VALID T SPICYC SCK (CPOL = 0) SCK (CPOL = 1) t MOSI DATA VALID ...
Page 59
... NXP Semiconductors 9.6.1 Texas Instruments synchronous serial mode (SSI mode) Table 23. Dynamic characteristic: SPI interface (SSI mode) − ° ° + (SUP3) over specified ranges. amb DD(IO) Symbol Parameter t SPI_MISO set-up time su(SPI_MISO) [1] Parameters are valid over operating temperature range unless otherwise specified. ...
Page 60
... NXP Semiconductors 2 9.7 I S-bus interface Table 24. Dynamic characteristics: I − ° ° +85 C for industrial applications amb Symbol Parameter common to input and output T clock cycle time cy(clk) t rise time r t fall time f output t pulse width HIGH WH t pulse width LOW WL t data output valid time ...
Page 61
... NXP Semiconductors I2SRX_BCK0 or I2SRX_BCK1 I2SRX_DATA0 or I2SRX_DATA1 I2SRX_WS0 or I2SRX_WS1 2 Fig 26. I S-bus timing (input) 2 9.8 I C-bus interface Table 25. Dynamic characteristics: I − ° ° [ +85 C. amb Symbol Parameter f SCL clock frequency SCL t output fall time f(o) t rise time r t fall time f t bus free time between a STOP and ...
Page 62
... NXP Semiconductors SDA t t BUF LOW SCL HD;STA Remark: Signals SDA and SCL correspond to pins I2C_SDAx and I2C_SCLx ( 1). 2 Fig 27. I C-bus pins clock timing 9.9 USB interface Table 26. Dynamic characteristics: USB pins (high-speed) Ω pF 1 DD(IO) Symbol Parameter t rise time ...
Page 63
... NXP Semiconductors T PERIOD crossover point differential data lines differential data to SE0/EOP skew n × T PERIOD Fig 28. Differential data-to-EOP transition skew and EOP width 9.10 10-bit ADC Table 27: Dynamic characteristics: 10-bit ADC Symbol Parameter f sampling frequency s t conversion time conv LPC3130_3131 Preliminary data sheet ...
Page 64
Application information Table 28. LCD panel connections TFBGA pin # Pin name K8 mLCD_CSB/EBI_NSTCS_0 L8 mLCD_E_RD/EBI_CKE P8 mLCD_RS/EBI_NDYCS N9 mLCD_RW_WR/EBI_DQM_1 N8 mLCD_DB_0/EBI_CLKOUT P9 mLCD_DB_1/EBI_NSTCS_1 ...
Page 65
... NXP Semiconductors 11. Marking Table 29. LPC3130/3131 Marking Line A LPC3130_3131 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Marking Description LPC3130/3131 BASIC_TYPE All information provided in this document is subject to legal disclaimers. Rev. 1.04 — 27 May 2010 LPC3130/3131 © NXP B.V. 2010. All rights reserved ...
Page 66
... NXP Semiconductors 12. Package outline TFBGA180: thin fine-pitch ball grid array package; 180 balls ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) UNIT 1.20 0.40 0.50 max 0.80 mm nom 1.06 0.35 0.71 0.45 min 0.95 0.30 0.65 0.40 OUTLINE ...
Page 67
... NXP Semiconductors 13. Abbreviations Table 30. Abbreviations Acronym A/D ADC AHB AMBA APB ATA BIU CE CGU CRC DFU DMA DRM DSP EBI ECC EOP ESD FIFO FPGA GF INTC IOCONFIG IOM IrDA IROM ISRAM ISROM JTAG LSB MCI MCU MMC MPMC OTG PCM PHY ...
Page 68
... NXP Semiconductors Table 30. Abbreviations Acronym RNG ROM SD SDHC SDIO SDR SE0 SIR SPI SSI SysCReg TAP TDO UART USB UTMI WDT LPC3130_3131 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers …continued Description Random Number Generator Read-Only Memory Secure Digital Secure Digital High Capacity ...
Page 69
... NXP Semiconductors 14. Revision history Table 31: Revision history Document ID Release date LPC3130_3131 v.1.04 <tbd> • Modifications: Reset state of JTAG pins and GPIO0, GPIO1, and GPIO2 pins updated in • Digital I/O level for pin CLOCK_OUT corrected in • USB-IF TestID numbers added in • Power consumption data updated in LPC3130_3131_1.03 < ...
Page 70
... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
Page 71
... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
Page 72
... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 2.1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . 13 6.1 ARM926EJ 6.2 Memory map 6.3 JTAG 6.4 NAND flash controller . . . . . . . . . . . . . . . . . . . 15 6.5 Multi-Port Memory Controller (MPMC ...