LPC3250FET296/01,5 NXP Semiconductors, LPC3250FET296/01,5 Datasheet - Page 35

• Manufacturer Part Number: LPC3250FET296/01,5
• Description: IC ARM9 MCU 256K 296-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC32x0r

Specifications of LPC3250FET296/01,5

• Package / Case: 296-TFBGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 266MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, Motor Control PWM, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: ROMless
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 3.6 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC32
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 256 KB
• Interface Type: EMC
• Maximum Clock Frequency: 266 MHz
• Number Of Timers: 6
• Operating Supply Voltage: 1.31 V to 1.39 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, DK-57TS-LPC3250, DK-57VTS-LPC3250, SOMDIMM-LPC3250
• Development Tools By Supplier: OM11016, OM11021, OM11045
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 3 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4962; 935290766551

NXP Semiconductors
LPC3220_30_40_50_1
Preliminary data sheet
7.8.2.1 Features
7.8.3.1 Features
7.8.3 SSP serial I/O controller
7.8.4 I
Only a single master and a single slave can communicate on the interface during a given
data transfer. During a data transfer the master always sends a byte of data to the slave,
and the slave always sends a byte of data to the master. The SPI implementation on the
LPC3220/30/40/50 does not support operation as a slave.
The LPC3220/30/40/50 contains two SSP controllers. The SSP controller is capable of
operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and
slaves on the bus. Only a single master and a single slave can communicate on the bus
during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits
to 16 bits of data flowing from the master to the slave and from the slave to the master. In
practice, often only one of these data flows carries meaningful data.
There are two I
can be configured as a master, multi-master or slave supporting up to 400 kHz. The I
blocks also support 7 or 10 bit addressing. Each has a four word FIFO for both transmit
and receive. An interrupt signal is available from each block.
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C-bus serial I/O controller
Supports slaves compatible with SPI modes 0 to 3.
Half duplex synchronous transfers.
DMA support for data transmit and receive.
1-bit to 16-bit word length.
Choice of LSB or MSB first data transmission.
64
Bit rates up to 52 Mbit/s.
Busy input function.
DMA time out interrupt to allow detection of end of reception when using DMA.
Timed interrupt to facilitate emptying the FIFO at the end of a transmission.
SPI clock and data pins may be used as general purpose pins if the SPI is not used.
Slave selects can be supported using GPO or GPIO pins
Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire
buses
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
Maximum SPI bus data bit rate of
clock rate
DMA transfers supported by GPDMA
16-bit input or output FIFO.
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C-bus interfaces in the LPC32x0 family of controllers. These I
Rev. 01 — 6 February 2009
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2
(Master mode) and
LPC3220/30/40/50
16/32-bit ARM microcontrollers
1
12
(Slave mode) of the input
© NXP B.V. 2009. All rights reserved.
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C blocks
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