LPC2365FBD100,551 NXP Semiconductors, LPC2365FBD100,551 Datasheet - Page 46
![IC ARM7 MCU FLASH 256K 100LQFP](/photos/6/65/66516/568-100-lqfp_sot407-1_sml.jpg)
LPC2365FBD100,551
Manufacturer Part Number
LPC2365FBD100,551
Description
IC ARM7 MCU FLASH 256K 100LQFP
Manufacturer
NXP Semiconductors
Series
LPC2300r
Datasheet
1.LPC2364FBD100551.pdf
(59 pages)
Specifications of LPC2365FBD100,551
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
Ethernet, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
58K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC23
Core
ARM7TDMI-S
Data Bus Width
32 bit
Data Ram Size
58 KB
Interface Type
CAN, I2C, I2S, SPI, SSP, UART, USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
On-chip Dac
10 bit, 1 Channel
Package
100LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
For Use With
568-4310 - EVAL BOARD LPC2158 W/LCDMCB2360UME - BOARD EVAL MCB2360 + ULINK-MEMCB2360U - BOARD EVAL MCB2360 + ULINK2568-4014 - BOARD EVAL FOR LPC236X ARM568-3999 - BOARD EVAL FOR LPC23 ARM MCU622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4409
935286017551
LPC2365FBD100-S
935286017551
LPC2365FBD100-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2365FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
LPC2365FBD100,551
Manufacturer:
NXP/恩智浦
Quantity:
20 000
NXP Semiconductors
LPC2364_65_66_67_68_6
Product data sheet
Fig 11. External clock timing (with an amplitude of at least V
Fig 12. Differential data-to-EOP transition skew and EOP width
Fig 13. MISO line set-up time in SSP Master mode
T
PERIOD
differential
data lines
10.1 Timing
MOSI
MISO
shifting edges
SCK
n × T
differential data to
crossover point
SE0/EOP skew
PERIOD
+ t
FDEOP
t
CHCL
Rev. 06 — 1 February 2010
t
su(SPI_MISO)
t
CLCX
crossover point
i(RMS)
T
extended
cy(clk)
= 200 mV)
t
CLCH
LPC2364/65/66/67/68
t
Single-chip 16-bit/32-bit microcontrollers
CHCX
sampling edges
002aaa907
source EOP width: t
receiver EOP width: t
002aad326
© NXP B.V. 2010. All rights reserved.
FEOPT
002aab561
EOPR1
, t
EOPR2
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